NXP Semiconductors XC7WH126DC,125
- Part No.:
- XC7WH126DC,125
- Manufacturer:
- NXP Semiconductors
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
XC7WH126DC,125.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 8VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
XC7WH126DC,125 from Nexperia is a dual non-inverting 3-state buffer/line driver in VSSOP8 package, operating from −40 °C to +125 °C with supply voltage range 2.0–5.5 V. It features symmetrical output impedance, balanced propagation delays (≤7.0 ns at 5 V/15 pF), and high noise immunity. Used for bidirectional bus interfacing in industrial control modules requiring level translation and output isolation.
For engineers reviewing the XC7WH126DC,125 datasheet, XC7WH126DC,125 pinout, XC7WH126DC,125 application, or XC7WH126DC,125 equivalent, key selection criteria include 3-state enable timing (ten ≤6.5 ns), ESD robustness (HBM >2000 V), thermal performance in compact VSSOP8, and compatibility with 3.3 V/5 V mixed-signal systems.
Technical Context
The XC7WH126DC,125 implements two independent CMOS buffer channels, each with active-low 3-state enable (nOE) controlling high-impedance output. Its Si-gate CMOS architecture ensures TTL-compatible input thresholds and rail-to-rail output swing under load.
Functional behavior follows strict truth table: when nOE = LOW, output Y mirrors input A; when nOE = HIGH, Y enters high-Z state regardless of A. Propagation delay symmetry (tPLH ≈ tPHL) and enable/disable time matching (tPZH ≈ tPLZ) support deterministic timing in synchronous data buses.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - supports direct interface with 2.5 V, 3.3 V, and 5 V logic families without level shifters |
| Propagation Delay (tpd) | ≤7.0 ns at VCC = 5.0 V, CL = 15 pF - enables reliable operation up to ~70 MHz bus toggle rates |
| 3-State Enable Time (ten) | ≤6.5 ns at VCC = 5.0 V, CL = 15 pF - ensures fast bus arbitration and minimal contention window |
| ESD Protection (HBM) | >2000 V - meets IEC 61000-4-2 Level 2 for board-level handling in industrial assembly |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive ECUs and industrial motor drives |
| Input Leakage Current | ≤2.0 μA at −40 °C to +125 °C - minimizes standby current in always-on sensor interfaces |
| Output Drive Strength | ±8 mA at VCC = 4.5 V - sufficient to drive 15 pF loads across PCB traces with <10 cm length |
Pinout & Package
VSSOP8 (SOT765-1) package: plastic very thin shrink small outline, 8 leads, body width 2.3 mm, lead pitch 0.5 mm, pin 1 indicator at lower-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 7 | 1OE, 2OE | Active-low 3-state enable inputs - simultaneous assertion disables both outputs to high-Z |
| 2, 5 | 1A, 2A | Buffer data inputs - TTL-compatible thresholds (VIL ≤0.9 V, VIH ≥2.1 V at 3 V) |
| 4 | GND | Ground reference - must be low-inductance connection to minimize switching noise coupling |
| 3, 6 | 1Y, 2Y | Non-inverting buffered outputs - rail-to-rail swing with symmetrical rise/fall times |
| 8 | VCC | Positive supply - decoupling capacitor (100 nF) required within 5 mm of this pin |
Key Features
| Feature | Design Value |
|---|---|
| Symmetrical output impedance | Ensures matched rise/fall times (<1 ns skew) critical for clean signal integrity on shared buses |
| Balanced propagation delays | tPLH and tPHL differ by <0.3 ns - eliminates duty-cycle distortion in clock distribution paths |
| High noise immunity | Input hysteresis >0.3 V at 3.3 V - suppresses false triggering from EFT bursts or crosstalk |
| Low power dissipation | ICC ≤40 μA at 125 °C - enables use in thermally constrained modules without forced cooling |
| Multiple package options | VSSOP8 (XC7WH126DC), TSSOP8 (XC7WH126DP), XSON8 (XC7WH126GD) - supports layout optimization across density tiers |
Applications
| Industrial PLC Backplane Interface | Automotive Body Control Module (BCM) |
|---|---|
Use Scenario: Isolating microcontroller GPIOs from noisy 24 V I/O expansion cards in modular PLC racks. IC Role / Device Role / Timing Role: Dual buffer provides direction-controlled signal routing between MCU and isolated CAN/LIN transceivers while enabling bus contention avoidance via 3-state control. Use Value: Enables hot-swap capability and prevents back-driving during card insertion/removal due to guaranteed high-Z state at power-up (nOE default HIGH). |
Use Scenario: Driving multiplexed LED indicators and relay drivers from an ASIL-B microcontroller in BCM head units. IC Role / Device Role / Timing Role: Acts as level-shifting buffer between 3.3 V MCU outputs and 5 V LED sink drivers, with 3-state allowing shared control lines across multiple LED banks. Use Value: Reduces component count vs discrete FET solutions and guarantees <100 ns disable time to meet ISO 16750-2 short-circuit transient response requirements. |
| Medical Patient Monitor Data Bus | Test Equipment Signal Conditioning |
Use Scenario: Buffering analog-to-digital converter (ADC) serial interface signals (SDO, SCLK) in portable ECG monitors. IC Role / Device Role / Timing Role: Provides noise-isolated, low-skew transmission of SPI clock/data between ADC and ARM Cortex-M4 host, with 3-state supporting multi-drop bus topology. Use Value: Maintains <1 ns inter-channel skew across temperature to preserve 16-bit ADC timing margins and prevent sample misalignment. |
Use Scenario: Conditioning digital stimulus signals from arbitrary waveform generators before injection into DUTs during functional test. IC Role / Device Role / Timing Role: Buffers and isolates test pattern generators from variable capacitive loads of different DUTs using 3-state to disconnect unused channels. Use Value: Eliminates need for manual reconfiguration; enables automated test sequencing with <5 ns channel switching latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DCUR | Lower VCC min (1.65 V), higher max drive (±24 mA), same VSSOP8 footprint | Better suited for battery-powered 1.8 V systems; less suitable for 5 V legacy interfaces | Select when operating below 2.0 V or requiring higher current drive; verify 5 V tolerance on inputs if interfacing with older logic. |
| 74AUP2G126GW,125 | Ultra-low power (ICC ≤0.9 μA), slower speed (tpd ≤11.4 ns), same VSSOP8 | Optimized for energy-constrained IoT edge nodes; not recommended for >25 MHz timing-critical paths | Select for always-on sensor hubs where sub-μA quiescent current outweighs speed requirements; avoid in real-time control loops. |
Compared with SN74LVC2G126DCUR and 74AUP2G126GW,125, the XC7WH126DC,125 delivers optimal balance of 5 V tolerance, 7 ns speed, and 125 °C operation-making it the preferred choice for industrial and automotive applications demanding robustness over ultra-low power or sub-2 V operation.
Availability
XC7WH126DC,125 is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive body control modules, medical patient monitor data buses, and test equipment signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for XC7WH126DC,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on automotive, industrial, computing, and consumer markets.
The XC7WH126DC,125 belongs to Nexperia's 7WH high-speed logic family, engineered for low-skew, high-noise-immunity buffering in space-constrained industrial and automotive control systems.
FAQ
What is the maximum operating frequency supported by the XC7WH126DC,125?
The XC7WH126DC,125 does not specify a maximum clock frequency directly, but its propagation delay (tpd ≤7.0 ns at 5 V/15 pF) and enable time (ten ≤6.5 ns) support reliable operation in systems with signal toggle rates up to approximately 70 MHz. Actual usable frequency depends on load capacitance, supply voltage, and PCB layout; for 50 pF loads, tpd increases to ≤9.5 ns, limiting practical use to ~50 MHz.
Does the XC7WH126DC,125 have built-in power-on reset behavior for the 3-state outputs?
Yes - the XC7WH126DC,125 outputs default to high-impedance (3-state OFF) at power-up because the output enable inputs (1OE, 2OE) are active-low and internally pulled weakly HIGH. This ensures no bus contention during system initialization. The device requires no external pull-up resistors for safe power sequencing, though external 10 kΩ pull-ups are recommended for noise immunity in electrically noisy environments.
Can the XC7WH126DC,125 operate with a 2.5 V supply voltage?
Yes - the XC7WH126DC,125 is fully specified down to 2.0 V supply voltage. At VCC = 2.5 V, VIH is guaranteed ≥1.7 V and VIL ≤0.75 V per datasheet Table 7, ensuring compatibility with 2.5 V logic families. Propagation delay increases to ≤9.5 ns (25 °C, 15 pF), and output drive strength reduces to ±4 mA, which remains sufficient for typical 2.5 V FPGA or microcontroller I/O loads.
What is the thermal resistance (RθJA) of the XC7WH126DC,125 in VSSOP8 package?
The datasheet specifies power derating for the VSSOP8 package: above 110 °C, total power dissipation (Ptot) decreases linearly at 8 mW/K. From this, RθJA is calculated as 125 K/W (since ΔT = P × RθJA). This value assumes standard JEDEC 2-layer board conditions; actual RθJA improves to ~80 K/W with 2 cm² copper pour under the package, enabling full 250 mW rating up to 100 °C ambient.
Is the XC7WH126DC,125 pin-compatible with other members of the XC7WH family?
Yes - all XC7WH126 variants (XC7WH126DC/VSSOP8, XC7WH126DP/TSSOP8, XC7WH126GD/XSON8) share identical pin functions and logic behavior. Pin 1 (1OE) through pin 8 (VCC) map identically across packages, enabling drop-in replacement during design iteration or cost optimization. However, mechanical dimensions and soldering profiles differ: VSSOP8 requires finer pitch reflow control than TSSOP8, and XSON8 needs stencil aperture adjustment for leadless mounting.
XC7WH126DC,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 7WH
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSSOP
XC7WH126DC,125 FAQ
1.How can I place an order for XC7WH126DC,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for XC7WH126DC,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC7WH126DC,125 reliable?
The price and inventory of XC7WH126DC,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC7WH126DC,125 is usually 5 days.
3.What payment methods are accepted for XC7WH126DC,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC7WH126DC,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XC7WH126DC,125?
XC7WH126DC,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XC7WH126DC,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC7WH126DC,125?
For technical support, including XC7WH126DC,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC7WH126DC,125 requirements.
6.How does Aetrix verify that XC7WH126DC,125 is sourced from the original manufacturer or authorized distributors?
All XC7WH126DC,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC7WH126DC,125 meets industry standards.
7.What is the process for return or replacement of XC7WH126DC,125?
All XC7WH126DC,125 units undergo pre-shipment inspection (PSI). If there is an issue with XC7WH126DC,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC7WH126DC,125 part is unused and in its original packaging.
Return procedure for XC7WH126DC,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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