Nexperia USA Inc. XC7WH126DP,125
- Part No.:
- XC7WH126DP,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
XC7WH126DP,125.pdf
- Description:
- IC BUF NON-INVERT 5.5V 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,000
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Product details
Overview
XC7WH126DP,125 from Nexperia is a dual non-inverting 3-state buffer/line driver in TSSOP8 (SOT505-2) package, designed for bidirectional bus interfacing and signal isolation in high-speed digital systems. It operates across -40 °C to +125 °C, supports 2.0–5.5 V supply, delivers ≤7.0 ns propagation delay at 3.3 V/15 pF, and features CMOS-compatible inputs with symmetrical output impedance.
For engineers reviewing the XC7WH126DP,125 datasheet, XC7WH126DP,125 pinout, XC7WH126DP,125 application, or XC7WH126DP,125 equivalent, key selection criteria include 3-state enable timing (≤9.5 ns disable time), rail-to-rail input voltage tolerance (−0.5 V to VCC+0.5 V), low ICC (≤40 μA), and industrial temperature range compliance.
Technical Context
The XC7WH126DP implements two independent non-inverting buffers, each with active-HIGH output enable (1OE, 2OE) controlling high-impedance OFF-state on corresponding outputs (1Y, 2Y). Inputs (1A, 2A) accept standard CMOS logic levels, and outputs drive capacitive loads up to 50 pF with matched rise/fall times.
Its architecture enables bus-hold-free signal routing in mixed-voltage systems: VCC defines logic thresholds (VIH = 3.85 V min at VCC = 5.5 V; VIL = 1.65 V max), while static current draw remains below 10 μA over full temperature range, supporting low-power standby modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage (VCC) | 2.0–5.5 V - Enables interoperability with 2.5 V, 3.3 V, and 5 V logic families without level shifters. |
| Propagation Delay (tpd) | ≤7.0 ns @ 3.3 V/15 pF - Supports >100 MHz data rates in point-to-point or lightly loaded bus applications. |
| Enable/Disable Time (ten/tdis) | ≤9.5 ns @ 3.3 V/50 pF - Ensures clean bus arbitration with minimal contention window during state transitions. |
| Output Drive Strength | ±8 mA @ VCC = 4.5 V - Sufficient to drive 50 Ω transmission lines or multiple CMOS inputs (fan-out ≥20). |
| Input Leakage Current | ≤2.0 μA @ −40 °C to +125 °C - Guarantees stable enable/disable control under extended thermal stress without pull-up/down burden. |
| ESD Robustness | HBM >2000 V, CDM >1000 V - Meets IEC 61000-4-2 Level 3 requirements for board-level handling and system integration. |
Pinout & Package
TSSOP8 package (SOT505-2): plastic thin shrink small outline, 8-pin, 3 mm body width, 0.65 mm pitch, lead length 0.5 mm, rated for −40 °C to +125 °C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 7 (1OE, 2OE) | Active-HIGH output enable | Drives respective output (1Y or 2Y) into high-Z when LOW; requires no external pull-down for default disabled state. |
| 2, 5 (1A, 2A) | Data input | CMOS-compatible input accepting VI from GND to VCC; 1.5 pF typical input capacitance minimizes loading on driving source. |
| 3, 6 (2Y, 1Y) | Data output | Non-inverting buffered output with symmetrical VOH/VOL and matched tPLH/tPHL for glitch-free signal replication. |
| 4 | GND | Signal and power reference plane; decoupling capacitor must be placed adjacent to Pin 4 and Pin 8 for noise suppression. |
| 8 | VCC | Primary supply rail; supports bypassing with 100 nF ceramic capacitor directly between Pins 4 and 8 to maintain switching stability. |
Key Features
| Feature | Design Value |
|---|---|
| Symmetrical output impedance | Enables matched rise/fall times (tr/tf ≤3 ns) and reduces signal distortion on mismatched PCB traces. |
| Balanced propagation delays | Ensures <100 ps skew between channels, critical for parallel data bus integrity and clock distribution buffering. |
| High noise immunity | VIH/VIL margins exceed 30% of VCC across full temperature range, rejecting EMI-induced false triggering in noisy industrial environments. |
| Low power dissipation | ICC ≤40 μA at VCC = 5.5 V enables use in always-on subsystems without thermal derating concerns. |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating microcontroller GPIOs from relay driver ICs and sensor ADCs in modular I/O racks. IC Role / Device Role / Timing Role: Dual 3-state buffer enabling time-multiplexed access to shared analog front-end and digital actuator buses. Use Value: Prevents bus contention during hot-swap events and allows firmware-controlled channel gating without external logic. |
Use Scenario: Level-shifting and isolating LIN bus transceiver control signals from 3.3 V MCU GPIOs in door module ECUs. IC Role / Device Role / Timing Role: Non-inverting buffer with fast enable/disable synchronizing wake-up commands and sleep-mode entry across distributed nodes. Use Value: Eliminates need for discrete MOSFET switches while meeting ISO 11898-3 timing constraints for LIN physical layer handshaking. |
| Medical Patient Monitor Data Bus | Test Equipment Signal Routing |
|
Use Scenario: Buffering serial interface signals (SPI, I²C) between isolated patient-side sensors and host-side processing units. IC Role / Device Role / Timing Role: 3-state line driver providing galvanic isolation boundary with controlled output impedance for EMI-compliant trace routing. Use Value: Maintains signal integrity across split-ground partitions while supporting <5 ns jitter margin required for 10 Mbps SPI diagnostics. |
Use Scenario: Multiplexing DUT test signals between FPGA-based pattern generators and measurement instruments in ATE fixtures. IC Role / Device Role / Timing Role: Dual-channel bidirectional buffer enabling reconfigurable signal path selection via FPGA-controlled OE pins. Use Value: Reduces fixture wiring complexity and eliminates mechanical relays, improving test repeatability and reducing maintenance downtime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DCUR | Same TSSOP8 footprint but lower VCC range (1.65–5.5 V); tpd = 3.7 ns @ 3.3 V/50 pF (faster), ICC = 10 μA (lower). | Optimized for battery-powered portable test gear requiring ultra-low quiescent current and sub-4 ns timing. | Select when operating below 2.0 V or needing tighter timing budgets; verify 1.65 V VIH compatibility with driving source. |
| 74AUP2G126GM,132 | VCC = 0.8–3.6 V only; tpd = 10.3 ns @ 3.0 V/50 pF (slower); ICC = 0.5 μA (ultra-low); −40 °C to +125 °C rated. | Targeted at energy-harvesting sensor nodes where sub-μA standby dominates design priority over speed. | Choose for sub-1 V logic domains or extreme low-power sleep modes; not suitable for 5 V systems or >50 MHz operation. |
Compared with SN74LVC2G126DCUR, XC7WH126DP,125 offers higher VCC tolerance (up to 5.5 V) and better noise margin at 5 V operation, while 74AUP2G126GM,132 trades speed for nanoampere-level ICC-making XC7WH126DP,125 the balanced choice for industrial 3.3/5 V mixed-signal interfaces.
Availability
XC7WH126DP,125 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, medical patient monitor data buses, and test equipment signal routing requiring stable component supply across extended temperature ranges.
Supply support for XC7WH126DP,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, high-reliability logic, analog, and discrete components for automotive, industrial, and consumer markets.
The XC7WH series targets high-speed, low-power 3-state buffering in space-constrained industrial and automotive applications, emphasizing robust ESD protection, wide VCC range, and guaranteed operation up to +125 °C.
FAQ
What is the maximum recommended load capacitance for reliable operation?
The datasheet specifies dynamic performance up to 50 pF load capacitance, with propagation delay increasing linearly beyond that value. At CL = 50 pF and VCC = 3.3 V, tpd remains ≤7.0 ns and tdis ≤9.5 ns-ensuring timing closure in most PCB interconnect scenarios. Exceeding 50 pF may require layout optimization or local termination.
Does XC7WH126DP,125 support mixed-voltage operation between input and output sides?
No-it is a single-supply device with all I/O referenced to the same VCC rail. Input voltage range is −0.5 V to VCC + 0.5 V, and output swing is rail-to-rail within VCC/GND. For true level translation, a dedicated dual-supply translator like NXH0108UK is required.
How does the 3-state enable timing affect bus arbitration in multi-driver systems?
With ten ≤9.5 ns and tdis ≤9.5 ns at 3.3 V/50 pF, the device ensures rapid transition between driven and high-Z states-minimizing bus contention windows to under 20 ns. This allows deterministic arbitration in systems with ≤50 ns clock periods, such as 20 MHz SPI or legacy parallel address/data buses.
Is thermal derating required for continuous operation at +125 °C ambient?
Yes-the TSSOP8 package (SOT505-2) derates total power dissipation linearly at 4.6 mW/K above +96 °C. At +125 °C, Ptot drops to ~120 mW. With typical ICC ≤40 μA and IO ≤8 mA, power dissipation stays well below this limit-no external heatsinking is needed for standard logic-level loading.
XC7WH126DP,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 7WH
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
XC7WH126DP,125 FAQ
1.How can I place an order for XC7WH126DP,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for XC7WH126DP,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC7WH126DP,125 reliable?
The price and inventory of XC7WH126DP,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC7WH126DP,125 is usually 5 days.
3.What payment methods are accepted for XC7WH126DP,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC7WH126DP,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XC7WH126DP,125?
XC7WH126DP,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XC7WH126DP,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC7WH126DP,125?
For technical support, including XC7WH126DP,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC7WH126DP,125 requirements.
6.How does Aetrix verify that XC7WH126DP,125 is sourced from the original manufacturer or authorized distributors?
All XC7WH126DP,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC7WH126DP,125 meets industry standards.
7.What is the process for return or replacement of XC7WH126DP,125?
All XC7WH126DP,125 units undergo pre-shipment inspection (PSI). If there is an issue with XC7WH126DP,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC7WH126DP,125 part is unused and in its original packaging.
Return procedure for XC7WH126DP,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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