AMD XC95108-20PQ160C
- Part No.:
- XC95108-20PQ160C
- Manufacturer:
- AMD
- Package:
- 160-BQFP
- Datasheet:
-
XC95108-20PQ160C.pdf
- Description:
- IC CPLD 108MC 20NS 160QFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,015
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Product details
Overview
XC95108-20PQ160C from AMD (acquired Xilinx CPLD business) is a 108-macrocell in-system programmable Complex Programmable Logic Device (CPLD) in a 160-pin PQFP package, with 5 ns pin-to-pin logic delay, 100% JTAG boundary-scan testability, and 5 V tolerant I/Os. It targets glue logic replacement and control logic in industrial PLCs, legacy interface bridging, and board-level state machine implementation.
For engineers reviewing the XC95108-20PQ160C datasheet, pinout, applications, or equivalent options, key selection factors include macrocell count, propagation delay, supply voltage range, JTAG compliance, and PQFP thermal/mounting compatibility.
Technical Context
The XC95108-20PQ160C implements a multi-array architecture with four function blocks, each containing 27 macrocells with configurable product-term sharing and buried register feedback. Each macrocell supports combinational or registered output with global/local clock, reset, set, and output enable controls.
It uses LVTTL-compatible I/Os operating at 5 V, supports IEEE Std 1149.1 JTAG for programming and boundary-scan testing, and features slew-rate controlled outputs to reduce EMI. Configuration is retained after power-down via on-chip EEPROM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Macrocells | 108 - provides logic density sufficient for medium-complexity control functions and bus interfacing |
| Propagation Delay | 5 ns - enables reliable operation in 100 MHz system timing paths |
| Supply Voltage | 5.0 V ± 10% - compatible with legacy 5 V TTL/CMOS systems without level shifting |
| I/O Pins | 132 user I/Os - supports wide parallel bus handling and multi-peripheral control |
| Package | PQFP-160 - 28 × 28 mm body, 0.65 mm pitch, standard reflow profile, RoHS-compliant |
| JTAG Support | IEEE 1149.1 compliant - enables in-circuit programming and production test without socketing |
Pinout & Package
PQFP-160 package with 20 × 20 pin grid, 0.65 mm pitch, and exposed thermal pad (non-electrical). Pin 1 marked by corner notch; pins numbered counter-clockwise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply | 5 V core and I/O supply; requires local 0.1 µF decoupling per VCC pin group |
| GND | Ground reference | Multiple dedicated ground pins distributed across all four sides for low-inductance return paths |
| TCK, TMS, TDI, TDO | JTAG interface | Enable boundary-scan test and in-system programming without external hardware programmers |
| TDI, TDO | JTAG data path | Support daisy-chain configuration for multi-device programming in dense PCB layouts |
| I/O[0..131] | Configurable bidirectional I/O | Each supports Schmitt-trigger input, slew-rate control, and programmable pull-up |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enables field firmware updates and design iteration without device removal or socket use |
| 100% IEEE 1149.1 JTAG testability | Reduces production test time and eliminates need for bed-of-nails fixtures in high-volume manufacturing |
| 5 ns pin-to-pin delay | Meets setup/hold timing for 100 MHz synchronous interfaces such as ISA, PC/104, and legacy microcontroller buses |
| Programmable slew-rate control | Minimizes signal overshoot/ringing on long traces or unterminated lines in industrial backplanes |
| On-chip EEPROM configuration memory | Eliminates external configuration PROM and associated boot-time delays; retains logic state across power cycles |
Applications
| Industrial Control Logic | Legacy Bus Interface |
|---|---|
Use Scenario: Replacing discrete TTL logic in programmable logic controllers for sequence control and interlock management. IC Role / Device Role / Timing Role: CPLD implementing synchronous state machines with deterministic 5 ns propagation delay. Use Value: Reduces component count by >70% versus 74-series logic while maintaining full 5 V compatibility and real-time response. | Use Scenario: Bridging between ISA-bus peripherals and modern microcontrollers in retro-computing or test equipment upgrades. IC Role / Device Role / Timing Role: Glue logic translating address strobes, I/O enables, and interrupt signals with precise timing alignment. Use Value: Enables direct connection without level shifters or timing buffers, preserving original bus cycle timing. |
| Board-Level State Machine | EEPROM-Based Configuration Hub |
Use Scenario: Managing power-up sequencing, FPGA configuration handoff, and fault monitoring in mixed-technology embedded boards. IC Role / Device Role / Timing Role: Standalone control unit with internal registers and asynchronous event detection. Use Value: Provides deterministic startup behavior independent of host processor boot order or firmware readiness. | Use Scenario: Storing and distributing configuration bits to multiple downstream devices (e.g., ADCs, DACs, sensors) during system initialization. IC Role / Device Role / Timing Role: Nonvolatile configuration manager with parallel output capability and glitch-free enable sequencing. Use Value: Eliminates external serial EEPROM and software driver overhead, reducing BOM and boot latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CPLD-based control logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCR3128XL-10VQ100C | 128 macrocells, 3.3 V core/I/O, VQFP-100 package, lower power but incompatible voltage | Requires level translation in 5 V systems; better suited for new 3.3 V designs with lower static current | Select only if migrating to 3.3 V infrastructure and accepting PCB redesign for smaller footprint |
| XC95216-15HQ208C | 216 macrocells, 15 ns delay, HQFP-208 package, higher pin count and larger board area | Provides headroom for future logic expansion but increases cost and thermal mass | Choose when additional macrocells and I/Os are required for next-generation board revisions |
Compared with XC95108-20PQ160C, the XCR3128XL-10VQ100C offers higher density at lower voltage but mandates system-level voltage conversion, while the XC95216-15HQ208C delivers scalability at the expense of board space and cost-making XC95108-20PQ160C optimal for stable 5 V legacy integration.
Availability
XC95108-20PQ160C is available at Aetrix Electronics and suitable for industrial control systems, legacy interface adapters, and board-level sequencing circuits requiring stable component supply and long-term obsolescence management.
Supply support for XC95108-20PQ160C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD acquired Xilinx's CPLD product line in 2022, continuing development and support of industry-standard 5 V CPLDs for legacy system maintenance.
The XC9500 family was originally designed for drop-in replacement of 74-series TTL logic and microcontroller peripheral decoding in industrial and telecom infrastructure.
FAQ
What is the maximum operating frequency supported by XC95108-20PQ160C?
The XC95108-20PQ160C guarantees 5 ns pin-to-pin logic delay, enabling reliable operation in synchronous systems up to 100 MHz. Its internal register-to-register performance supports clock frequencies up to 125 MHz under typical conditions, but system-level timing must account for board trace delays and fanout loading. The XC95108-20PQ160C datasheet specifies worst-case tCO and tSU values referenced to the 5 ns speed grade.
Does XC95108-20PQ160C require an external configuration PROM?
No. The XC95108-20PQ160C contains on-chip EEPROM that retains configuration bitstream after power removal. It powers up fully operational without external configuration devices or host processor intervention. This eliminates boot dependencies and reduces BOM cost-key for standalone XC95108-20PQ160C deployments in industrial controllers.
Can XC95108-20PQ160C be reprogrammed in the system?
Yes. The XC95108-20PQ160C supports full in-system programmability via its IEEE 1149.1 JTAG interface. Reprogramming can be performed live on powered boards using standard JTAG cables and AMD/Xilinx iMPACT or Vivado tools-no socket or UV eraser required. This capability is integral to the XC95108-20PQ160C architecture and verified in production test.
What is the I/O voltage tolerance of XC95108-20PQ160C?
The XC95108-20PQ160C features 5 V-tolerant I/Os compatible with LVTTL and TTL signaling standards. Inputs accept 0–5.5 V, outputs drive to 5 V levels, and the device operates from a single 5.0 V ± 10% supply. This ensures seamless interoperability with legacy 5 V microcontrollers, FPGAs, and peripheral ICs without level-shifting circuitry.
Is XC95108-20PQ160C RoHS compliant?
Yes. The XC95108-20PQ160C PQFP-160 package is RoHS-6 compliant (lead-free terminations, no restricted substances above threshold limits). It meets JEDEC J-STD-020 moisture sensitivity level 3 and is qualified for standard Pb-free reflow profiles. Full compliance documentation is available in the official XC95108-20PQ160C product change notice archive.
XC95108-20PQ160C Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- XC9500
- Package/Case:
- 160-BQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- In System Programmable (min 10K program/erase cycles)
- Delay Time tpd(1) Max:
- 20 ns
- Voltage Supply - Internal:
- 4.75V ~ 5.25V
- Number of Logic Elements/Blocks:
- 6
- Number of Macrocells:
- 108
- Number of Gates:
- 2400
- Number of I/O:
- 108
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 160-PQFP (28x28)
XC95108-20PQ160C FAQ
1.How can I place an order for XC95108-20PQ160C through Aetrix?
Please submit a Request for Quotation (RFQ) for XC95108-20PQ160C on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC95108-20PQ160C reliable?
The price and inventory of XC95108-20PQ160C are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC95108-20PQ160C is usually 5 days.
3.What payment methods are accepted for XC95108-20PQ160C?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC95108-20PQ160C transactions.
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4.How is shipping managed for XC95108-20PQ160C?
XC95108-20PQ160C orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XC95108-20PQ160C order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC95108-20PQ160C?
For technical support, including XC95108-20PQ160C datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC95108-20PQ160C requirements.
6.How does Aetrix verify that XC95108-20PQ160C is sourced from the original manufacturer or authorized distributors?
All XC95108-20PQ160C products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC95108-20PQ160C meets industry standards.
7.What is the process for return or replacement of XC95108-20PQ160C?
All XC95108-20PQ160C units undergo pre-shipment inspection (PSI). If there is an issue with XC95108-20PQ160C, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC95108-20PQ160C part is unused and in its original packaging.
Return procedure for XC95108-20PQ160C:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XC95108-20PQ160C Tags

-
5M40ZE64C5N
Intel

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ATF1502ASV-15AU44
Microchip Technology

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5M80ZE64C5N
Intel

-
5M80ZT100C5N
Intel

-
ATF1502AS-10AU44
Microchip Technology

-
ATF1502AS-10JU44
Microchip Technology

-
5M80ZE64I5N
Intel

-
5M80ZT100I5N
Intel
-
LC4032V-75TN48C
Lattice Semiconductor Corporation

-
ATF1504ASV-15AU44
Microchip Technology

-
ATF1504AS-10JU44
Microchip Technology

-
5M160ZE64C5N
Intel
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