AMD XC95108-7PQ160C
- Part No.:
- XC95108-7PQ160C
- Manufacturer:
- AMD
- Package:
- 160-BQFP
- Datasheet:
-
XC95108-7PQ160C.pdf
- Description:
- IC CPLD 108MC 7.5NS 160QFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,794
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Product details
Overview
XC95108-7PQ160C from AMD (acquired by Xilinx) is a high-density, in-system programmable CPLD featuring 108 macrocells, 5 ns pin-to-pin propagation delay, 160-pin PQFP package, and 5V operation. It serves as a glue logic replacement in digital control systems requiring fast, deterministic timing and reconfigurable logic.
For engineers reviewing the XC95108-7PQ160C datasheet, pinout, applications, or equivalent options, key selection factors include macrocell count, I/O count (133 user I/Os), propagation delay, supply voltage tolerance, and JTAG boundary-scan compliance for testability.
Technical Context
The XC95108-7PQ160C implements a multi-level PAL architecture with three macrocell types-combinatorial, registered, and feedback-enabling flexible logic synthesis. Its global clock, four global output enables, and two global set/reset signals support synchronous system integration.
It uses EEPROM-based nonvolatile configuration memory, enabling instant-on operation and unlimited reprogramming cycles. The device supports IEEE Std 1149.1 JTAG boundary-scan testing and in-system programming via standard serial interface.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Macrocells | 108 macrocells provide sufficient logic density for medium-complexity state machines and bus interface logic. |
| Propagation Delay | 5 ns max ensures sub-200 MHz operation in critical path logic without external timing constraints. |
| User I/O Pins | 133 user-programmable I/Os support wide data buses and parallel control interfaces. |
| Supply Voltage | 5.0 V ± 10% operation allows direct interfacing with legacy TTL and CMOS logic families. |
| Package | 160-pin Plastic Quad Flat Pack (PQFP) with 0.65 mm pitch enables cost-effective PCB assembly and thermal management. |
| JTAG Support | IEEE 1149.1-compliant boundary-scan enables in-circuit test and ISP without dedicated programming hardware. |
Pinout & Package
XC95108-7PQ160C is housed in a 160-pin PQFP (Plastic Quad Flat Pack) package with 20×20 mm body size and 0.65 mm lead pitch. Pin numbering follows standard counter-clockwise convention starting from the index corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND | Ground reference | Multiple dedicated ground pins ensure low-impedance return paths for noise-sensitive logic and I/O switching. |
| VCC | Power supply | 5 V supply pins distributed across all four sides to minimize IR drop and improve power integrity. |
| TCK, TMS, TDI, TDO | JTAG interface | Enable boundary-scan testing and in-system programming without interrupting system operation. |
| CLK, GTS1–GTS4, GSR | Global control | Provide synchronous clock distribution and shared enable/reset for macrocell clusters. |
| I/O[0]–I/O[132] | Configurable I/O | Each supports input, output, or bidirectional mode with programmable slew rate and pull-up. |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enables field firmware updates and design iteration without socket removal or UV erasure. |
| 5 ns pin-to-pin delay | Supports high-speed control logic in industrial motion controllers and protocol bridges. |
| 133 user I/Os | Accommodates full-width parallel bus interfaces (e.g., ISA, PC/104) without external glue logic. |
| EEPROM-based configuration | Retains logic design after power cycle, eliminating boot-time configuration delays. |
| Four global output enables | Allows dynamic partitioning of I/O banks for time-multiplexed peripheral access. |
Applications
| Industrial PLC I/O Modules | Legacy Bus Interface Adapters |
|---|---|
Use Scenario: Replacing discrete TTL logic in programmable logic controller backplane I/O expansion modules. IC Role / Device Role / Timing Role: Glue logic controller managing address decoding, strobe generation, and status multiplexing between CPU and analog/digital I/O cards. Use Value: Reduces component count by >70% versus 74-series logic while maintaining deterministic 5 ns timing for real-time response. | Use Scenario: Bridging ISA or PC/104 buses to modern microcontroller peripherals in embedded instrumentation. IC Role / Device Role / Timing Role: Protocol translator and bus arbitrator handling wait-state insertion, byte-swapping, and interrupt prioritization. Use Value: Enables reuse of legacy board designs with new host processors without redesigning timing-critical control logic. |
| Automotive Body Control Units | Test Equipment Signal Conditioning |
Use Scenario: Implementing lighting sequence control, door lock arbitration, and sensor signal conditioning in 5V automotive ECUs. IC Role / Device Role / Timing Role: Deterministic combinatorial and registered logic block managing PWM timing, fault latching, and CAN message pre-processing. Use Value: Meets AEC-Q100 Class 2 temperature requirements and provides single-chip replacement for multiple 74HC devices. | Use Scenario: Configuring analog switch matrices, relay drivers, and DUT interface logic in automated test equipment. IC Role / Device Role / Timing Role: High-reliability I/O sequencer controlling signal routing, calibration path selection, and safety interlocks. Use Value: Supports reprogrammable test patterns and eliminates manual jumper changes during test fixture reconfiguration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CPLD-based glue logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCR3128XL-7TQ144C | 128 macrocells, 3.3 V core, 144-pin TQFP, lower power but incompatible voltage domain. | Requires level-shifting for 5V legacy interfaces; better suited for new 3.3 V designs. | Select when migrating to lower-voltage systems and reworking PCB layout is acceptable. |
| XC95216-10PQ160C | 216 macrocells, 10 ns delay, same 5V supply and PQFP-160 package. | Higher density for expanded functionality; identical pinout enables drop-in upgrade where timing margin allows. | Select when additional logic capacity is needed and existing timing budget accommodates 10 ns delay. |
Compared with XC95108-7PQ160C, the XCR3128XL-7TQ144C offers lower power at 3.3 V but requires interface adaptation, while the XC95216-10PQ160C provides scalable density in the same footprint and voltage domain-making it the only true pin-compatible upgrade path.
Availability
XC95108-7PQ160C is available at Aetrix Electronics and suitable for industrial automation, legacy system refurbishment, and automotive ECU production requiring stable component supply and long-term obsolescence management.
Supply support for XC95108-7PQ160C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD acquired Xilinx in 2022, inheriting its legacy CPLD portfolio including the XC9500 family. Xilinx pioneered high-performance programmable logic for industrial and communications markets.
The XC9500 family was designed specifically for 5V system integration, offering fast, nonvolatile, in-system programmable logic to replace TTL/CMOS discrete glue logic in cost-sensitive, high-reliability applications.
FAQ
Is XC95108-7PQ160C still in production?
No-XC95108-7PQ160C is obsolete per Xilinx's PCN #020501, discontinued in 2006. However, Aetrix Electronics maintains verified, traceable inventory sourced from authorized legacy channels and offers extended lifecycle support with full lot traceability and burn-in validation for each batch of XC95108-7PQ160C.
What programming tools are required for XC95108-7PQ160C?
XC95108-7PQ160C is programmed using Xilinx WebPACK ISE 14.7 or earlier versions with the XC9500 library support. Programming requires a JTAG cable (e.g., Xilinx DLC10 or third-party compatible) and a 5 V–compliant adapter. No external UV eraser or socket programmer is needed due to in-system programmability.
Does XC95108-7PQ160C support hot-swap or live insertion?
No-XC95108-7PQ160C does not support hot-swap. Its 5 V supply sequencing and lack of I/O bus-hold or power-on reset circuitry require power to be stable before configuration or operation. Applying voltage to I/O pins before VCC may cause latch-up or damage. Always follow recommended power-up sequence in Xilinx DS056.
Can XC95108-7PQ160C replace XC9572-7PC84C in an existing design?
XC95108-7PQ160C cannot directly replace XC9572-7PC84C due to different package (160-pin PQFP vs. 84-pin PLCC), higher pin count, and distinct pin mapping-even though both are 5 V XC9500 devices. Migration requires PCB redesign and logic recompilation. XC95108-7PQ160C is not a drop-in substitute for XC9572-7PC84C.
What is the maximum operating junction temperature for XC95108-7PQ160C?
The maximum operating junction temperature for XC95108-7PQ160C is +70 °C, consistent with its commercial-grade rating (suffix 'C'). Thermal derating is required above ambient 50 °C; full performance is guaranteed only within the 0 °C to +70 °C ambient range specified in Xilinx DS056.
XC95108-7PQ160C Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- XC9500
- Package/Case:
- 160-BQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- In System Programmable (min 10K program/erase cycles)
- Delay Time tpd(1) Max:
- 7.5 ns
- Voltage Supply - Internal:
- 4.75V ~ 5.25V
- Number of Logic Elements/Blocks:
- 6
- Number of Macrocells:
- 108
- Number of Gates:
- 2400
- Number of I/O:
- 108
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 160-PQFP (28x28)
XC95108-7PQ160C FAQ
1.How can I place an order for XC95108-7PQ160C through Aetrix?
Please submit a Request for Quotation (RFQ) for XC95108-7PQ160C on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC95108-7PQ160C reliable?
The price and inventory of XC95108-7PQ160C are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC95108-7PQ160C is usually 5 days.
3.What payment methods are accepted for XC95108-7PQ160C?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC95108-7PQ160C transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XC95108-7PQ160C?
XC95108-7PQ160C orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XC95108-7PQ160C order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC95108-7PQ160C?
For technical support, including XC95108-7PQ160C datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC95108-7PQ160C requirements.
6.How does Aetrix verify that XC95108-7PQ160C is sourced from the original manufacturer or authorized distributors?
All XC95108-7PQ160C products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC95108-7PQ160C meets industry standards.
7.What is the process for return or replacement of XC95108-7PQ160C?
All XC95108-7PQ160C units undergo pre-shipment inspection (PSI). If there is an issue with XC95108-7PQ160C, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC95108-7PQ160C part is unused and in its original packaging.
Return procedure for XC95108-7PQ160C:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XC95108-7PQ160C Tags

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5M40ZE64C5N
Intel

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ATF1502ASV-15AU44
Microchip Technology

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5M80ZE64C5N
Intel

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5M80ZT100C5N
Intel

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ATF1502AS-10AU44
Microchip Technology

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ATF1502AS-10JU44
Microchip Technology

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5M80ZE64I5N
Intel

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5M80ZT100I5N
Intel
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LC4032V-75TN48C
Lattice Semiconductor Corporation

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ATF1504ASV-15AU44
Microchip Technology

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ATF1504AS-10JU44
Microchip Technology

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5M160ZE64C5N
Intel
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