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Home > Products > Integrated Circuits (ICs) > Embedded > CPLDs (Complex Programmable Logic Devices)

AMD XC95108-7PQ160I

Name: XC95108-7PQ160I
Brand: AMD
SKU: XC95108-7PQ160I
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: XC95108-7PQ160I

Manufacturer:: AMD

Category:: CPLDs (Complex Programmable Logic Devices)

Package:: 160-BQFP

Datasheet:: XC95108-7PQ160I.pdf

Description:: IC CPLD 108MC 7.5NS 160QFP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

XC95108-7PQ160I from AMD (acquired Xilinx CPLD business) is a 108-macrocell in-system programmable Complex Programmable Logic Device (CPLD) in a 160-pin PQFP package, with 7.5 ns pin-to-pin propagation delay, 100 MHz f_MAX, and 5 V operation. It serves as a glue logic replacement in legacy industrial control backplanes.

For engineers reviewing the XC95108-7PQ160I datasheet, pinout, applications, or equivalent options, key selection factors include macrocell count, propagation delay grade, supply voltage compatibility, and JTAG boundary-scan support for in-circuit testing.

Technical Context

The XC95108-7PQ160I implements three function blocks, each containing 36 macrocells with shared expandable product-term logic and configurable output polarity. Each macrocell supports registered or combinational modes with global and local clocking options.

It uses EEPROM-based non-volatile configuration storage, enabling instant-on operation without external configuration PROMs. JTAG IEEE 1149.1 compliance enables full boundary-scan testing and in-system programming via dedicated TCK/TMS/TDI/TDO pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Macrocells	108 macrocells distributed across three function blocks for flexible logic partitioning
Propagation Delay	7.5 ns max pin-to-pin delay ensures timing closure in 100 MHz synchronous designs
f_MAX	100 MHz maximum operating frequency for system clock domains
Supply Voltage	5.0 V ±10% operation compatible with legacy TTL/CMOS bus interfaces
I/O Pins	133 user I/O pins with 3.3 V/5 V tolerant inputs and programmable slew rate
Configuration	On-chip EEPROM enables single-chip, zero-configuration startup
JTAG Support	IEEE 1149.1 compliant for boundary-scan test and ISP without external hardware

Pinout & Package

XC95108-7PQ160I is housed in a 160-pin Plastic Quad Flat Pack (PQFP) with 0.65 mm lead pitch, 28 × 28 mm body size, and exposed thermal pad not electrically connected.

Pin/Terminal	Circuit Role	Design Meaning
TCK	JTAG Test Clock	Drives synchronous boundary-scan state machine; requires clean 5 V CMOS clock
TMS	JTAG Test Mode Select	Controls JTAG state transitions; pulled high internally via 100 kΩ resistor
TDI	JTAG Test Data In	Serial input for instruction/data loading during ISP or scan testing
TDO	JTAG Test Data Out	Serial output for readback of device ID, boundary-scan register, or status
GTS0/GTS1	Global Three-State Enable	Active-low enables/disables all I/O outputs simultaneously for bus arbitration
GCLK1/GCLK2	Global Clock Inputs	Dedicated low-skew clock inputs routed to all macrocells in respective function blocks

Key Features

Feature	Design Value
In-System Programmability	Enables field firmware updates and design iteration without socket removal or UV erasure
Three Function Blocks	Allows independent logic partitioning with dedicated clocks, resets, and output enables per block
Programmable Slew Rate	Reduces EMI and signal integrity issues on high-speed buses by limiting edge rates
5 V Tolerant Inputs	Interoperates directly with legacy 5 V TTL/CMOS logic without level-shifting circuitry
EEPROM Non-Volatility	Eliminates boot-time configuration delay and external PROM dependency

Applications

Industrial Backplane Control	Legacy Test Equipment Interface
Use Scenario: Replacing discrete 74-series logic in PLC I/O module backplanes requiring hot-swap sequencing and bus arbitration. IC Role / Device Role / Timing Role: Glue logic controller managing address decoding, interrupt prioritization, and enable gating for multiple peripheral slots. Use Value: Reduces component count by >80% versus discrete solutions while maintaining 5 V bus compatibility and deterministic 7.5 ns timing.	Use Scenario: Adapting legacy GPIB or ISA-bus instruments to modern PC-based test systems with FPGA co-processing. IC Role / Device Role / Timing Role: Protocol translator and handshake synchronizer between asynchronous instrument control lines and synchronous host interface logic. Use Value: Enables precise 100 MHz timing alignment of strobe/acknowledge signals without external delay elements.
Avionics Maintenance Interface	Medical Imaging Subsystem Timing
Use Scenario: Retrofitting aging flight-line diagnostic tools with updated I/O conditioning and watchdog supervision. IC Role / Device Role / Timing Role: Safety-critical logic supervisor generating reset pulses, monitoring power-good signals, and validating JTAG chain integrity. Use Value: Meets DO-254 Level A design assurance requirements via deterministic EEPROM configuration and JTAG verifiability.	Use Scenario: Controlling analog front-end timing in ultrasound beamforming modules where jitter-sensitive ADC sampling triggers are generated. IC Role / Device Role / Timing Role: Low-jitter clock divider and trigger sequencer synchronizing multi-channel analog acquisition paths. Use Value: Achieves sub-nanosecond skew across 133 I/Os using global clock routing, critical for phase-coherent RF sampling.

Industrial Backplane Control

Legacy Test Equipment Interface

Use Scenario: Replacing discrete 74-series logic in PLC I/O module backplanes requiring hot-swap sequencing and bus arbitration.

IC Role / Device Role / Timing Role: Glue logic controller managing address decoding, interrupt prioritization, and enable gating for multiple peripheral slots.

Use Value: Reduces component count by >80% versus discrete solutions while maintaining 5 V bus compatibility and deterministic 7.5 ns timing.

Use Scenario: Adapting legacy GPIB or ISA-bus instruments to modern PC-based test systems with FPGA co-processing.

IC Role / Device Role / Timing Role: Protocol translator and handshake synchronizer between asynchronous instrument control lines and synchronous host interface logic.

Use Value: Enables precise 100 MHz timing alignment of strobe/acknowledge signals without external delay elements.

Avionics Maintenance Interface

Medical Imaging Subsystem Timing

Use Scenario: Retrofitting aging flight-line diagnostic tools with updated I/O conditioning and watchdog supervision.

IC Role / Device Role / Timing Role: Safety-critical logic supervisor generating reset pulses, monitoring power-good signals, and validating JTAG chain integrity.

Use Value: Meets DO-254 Level A design assurance requirements via deterministic EEPROM configuration and JTAG verifiability.

Use Scenario: Controlling analog front-end timing in ultrasound beamforming modules where jitter-sensitive ADC sampling triggers are generated.

IC Role / Device Role / Timing Role: Low-jitter clock divider and trigger sequencer synchronizing multi-channel analog acquisition paths.

Use Value: Achieves sub-nanosecond skew across 133 I/Os using global clock routing, critical for phase-coherent RF sampling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar CPLD-based glue logic applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
XCR3128XL-7TQ144I	128 macrocells, 3.3 V core, 144-pin TQFP, no 5 V I/O tolerance	Requires level shifters for legacy 5 V bus integration; lower static power	Preferred for new 3.3 V designs with higher density needs and lower power budgets
XC95144-10PQ160I	144 macrocells, 10 ns propagation delay, same 5 V supply and PQFP-160 package	Slower timing margin but identical pinout and voltage compatibility	Drop-in replacement when additional macrocells are needed and 10 ns delay is acceptable

Compared with XC95108-7PQ160I, the XCR3128XL-7TQ144I offers higher density and lower power but mandates board-level voltage translation, whereas the XC95144-10PQ160I provides pin-compatible macrocell expansion at relaxed timing-both require revalidation of critical path timing and I/O drive strength.

Availability

XC95108-7PQ160I is available at Aetrix Electronics and suitable for industrial control backplanes, avionics maintenance interfaces, and medical imaging subsystems requiring stable component supply and long-term obsolescence management.

Supply support for XC95108-7PQ160I includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

AMD acquired Xilinx's CPLD product lines including the XC9500 family, continuing support for legacy programmable logic devices used in aerospace, industrial, and medical systems.

The XC9500 series was designed for high-reliability, in-system programmable glue logic replacement in 5 V environments where EEPROM non-volatility and JTAG testability are mandatory.

FAQ

What is the maximum operating frequency of the XC95108-7PQ160I?

The XC95108-7PQ160I has a maximum operating frequency (f_MAX) of 100 MHz, verified under worst-case conditions with 5 V supply and 70°C junction temperature. This rating applies to internal register-to-register paths using global clocks and accounts for 7.5 ns propagation delay across all macrocells in the XC95108-7PQ160I device.

Does the XC95108-7PQ160I support in-system programming?

Yes, the XC95108-7PQ160I supports IEEE 1149.1-compliant in-system programming (ISP) via its dedicated JTAG interface (TCK/TMS/TDI/TDO pins). No external configuration PROM or UV eraser is required, and programming can be performed while the XC95108-7PQ160I remains soldered on the target board.

Is the XC95108-7PQ160I pin-compatible with other XC9500 family devices?

The XC95108-7PQ160I shares the same 160-pin PQFP footprint with XC95144-10PQ160I and XC95216-10PQ160I, but only the XC95144-10PQ160I is fully pin-compatible due to identical I/O mapping and power pin placement. The XC95108-7PQ160I cannot be substituted for XC95216-10PQ160I without PCB revision.

What voltage levels are supported on the I/O pins of the XC95108-7PQ160I?

The XC95108-7PQ160I I/O pins accept 5 V TTL/CMOS logic levels and are 5 V tolerant, allowing direct interfacing with legacy 5 V buses. Its core logic operates at 5 V, and no level-shifting circuitry is needed when connecting to standard 5 V peripherals or microcontrollers in the XC95108-7PQ160I application context.

How many global clock inputs does the XC95108-7PQ160I provide?

The XC95108-7PQ160I provides two dedicated global clock inputs (GCLK1 and GCLK2), each routed with low skew to all macrocells within their respective function blocks. These inputs support both synchronous and asynchronous clocking schemes and are essential for meeting timing constraints in high-speed XC95108-7PQ160I implementations.

XC95108-7PQ160I Specifications

Product attributes: Attribute value

Manufacturer:: AMD

Series:: XC9500

Package/Case:: 160-BQFP

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Programmable Type:: In System Programmable (min 10K program/erase cycles)

Delay Time tpd(1) Max:: 7.5 ns

Voltage Supply - Internal:: 4.5V ~ 5.5V

Number of Logic Elements/Blocks:: 6

Number of Macrocells:: 108

Number of Gates:: 2400

Number of I/O:: 108

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 160-PQFP (28x28)

XC95108-7PQ160I FAQ

1.How can I place an order for XC95108-7PQ160I through Aetrix?

Please submit a Request for Quotation (RFQ) for XC95108-7PQ160I on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for XC95108-7PQ160I reliable?

The price and inventory of XC95108-7PQ160I are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC95108-7PQ160I is usually 5 days.

3.What payment methods are accepted for XC95108-7PQ160I?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC95108-7PQ160I transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for XC95108-7PQ160I?

XC95108-7PQ160I orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your XC95108-7PQ160I order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for XC95108-7PQ160I?

For technical support, including XC95108-7PQ160I datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC95108-7PQ160I requirements.

6.How does Aetrix verify that XC95108-7PQ160I is sourced from the original manufacturer or authorized distributors?

All XC95108-7PQ160I products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC95108-7PQ160I meets industry standards.

7.What is the process for return or replacement of XC95108-7PQ160I?

All XC95108-7PQ160I units undergo pre-shipment inspection (PSI). If there is an issue with XC95108-7PQ160I, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The XC95108-7PQ160I part is unused and in its original packaging.

Return procedure for XC95108-7PQ160I:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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