AMD XC95144XL-7TQG100I
- Part No.:
- XC95144XL-7TQG100I
- Manufacturer:
- AMD
- Package:
- 100-LQFP
- Datasheet:
-
XC95144XL-7TQG100I.pdf
- Description:
- IC CPLD 144MC 7.5NS 100TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:6,156
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Product details
Overview
XC95144XL-7TQG100I from AMD (acquired Xilinx CPLD division) is a 144-macrocell in-system programmable CPLD with 100-pin TQFP package, 7.5 ns pin-to-pin propagation delay, 3.3 V supply, and IEEE 1149.1 JTAG boundary-scan support - used in legacy industrial control logic replacement and FPGA configuration glue logic.
For engineers reviewing the XC95144XL-7TQG100I datasheet, pinout, applications, or equivalent options, key selection criteria include macrocell count, propagation delay grade, JTAG compliance, I/O voltage tolerance, and legacy design migration path.
Technical Context
This CPLD implements a multi-array architecture with five function blocks, each containing 18 macrocells with product-term-based logic and registered outputs. It supports in-system programming via JTAG using IEEE 1149.1-compliant TCK/TMS/TDI/TDO signals and operates across –40°C to +85°C industrial temperature range.
Logic density is fixed at 144 macrocells with 111 user I/O pins, configurable output slew rate, and programmable ground/weak pull-up on all I/Os. The device uses non-volatile EEPROM for configuration retention without external memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Macrocell Count | 144 macrocells - defines maximum combinational/registered logic capacity for state machines and glue logic. |
| Propagation Delay | 7.5 ns - guarantees timing closure for 133 MHz system clock domains in synchronous designs. |
| Supply Voltage | 3.3 V ±0.3 V - requires dedicated 3.3 V rail; not 5 V tolerant. |
| I/O Pins | 111 user I/Os - supports wide bus interfacing and parallel control signal routing. |
| Operating Temp | –40°C to +85°C - validated for industrial environments without derating. |
| JTAG Support | IEEE 1149.1 compliant - enables boundary-scan testing and in-circuit programming without socketing. |
Pinout & Package
100-lead Thin Quad Flat Package (TQFP), 14 mm × 14 mm, 0.5 mm pitch, lead-free (RoHS-compliant), thermal pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Core power supply | 3.3 V main supply for logic array and macrocells; decoupling required per datasheet layout guidelines. |
| GND | Ground reference | Common return for all I/O and core logic; multiple GND pins reduce ground bounce. |
| TCK, TMS, TDI, TDO | JTAG test interface | Enable IEEE 1149.1 boundary-scan and ISP; no external programming hardware needed beyond JTAG adapter. |
| I/O[0:110] | Configurable bidirectional I/O | Supports TTL/LVCMOS 3.3 V signaling; individually programmable as input, output, or bidirectional with weak pull-up. |
| CLKIN | Global clock input | Dedicated low-skew input for synchronous logic; feeds global clock network to all function blocks. |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enables field firmware updates and logic revisions without device removal or socketing. |
| Five function blocks | Provides modular logic partitioning - each block handles independent control paths or state machines. |
| Programmable slew rate | Reduces EMI and signal integrity issues by limiting edge rates on high-speed I/O transitions. |
| Non-volatile EEPROM | Retains configuration after power cycle - no boot ROM or external PROM required. |
| Industrial temperature range | Validated operation from –40°C to +85°C - suitable for uncontrolled cabinet environments. |
Applications
| Industrial PLC I/O Expansion | FPGA Configuration Sequencing |
|---|---|
Use Scenario: Adding discrete digital I/O channels to legacy programmable logic controllers with space-constrained PCBs. IC Role / Device Role / Timing Role: Glue logic CPLD managing parallel address/data strobes, interrupt arbitration, and status encoding. Use Value: Replaces discrete 74-series logic with single-chip solution, reducing BOM count and board area by >60%. | Use Scenario: Controlling power-up sequence and configuration bitstream loading for Xilinx Spartan FPGAs. IC Role / Device Role / Timing Role: State-machine-based sequencer generating precise reset, INIT_B, and CCLK timing windows. Use Value: Ensures FPGA configuration reliability under varying supply ramp rates and ambient temperatures. |
| Legacy System Bus Interface | Test Equipment Control Logic |
Use Scenario: Adapting ISA or PC/104 bus signals to modern microcontroller peripherals in retro instrumentation upgrades. IC Role / Device Role / Timing Role: Address decoding, chip select generation, and wait-state insertion for asynchronous bus cycles. Use Value: Maintains compatibility with 8-bit/16-bit legacy peripherals while enabling MCU integration. | Use Scenario: Managing trigger synchronization, channel enable/disable, and calibration signal routing in automated test systems. IC Role / Device Role / Timing Role: Deterministic combinatorial logic for real-time stimulus/response coordination across multiple instruments. Use Value: Achieves sub-10 ns timing alignment between DUT interface and measurement capture subsystems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CPLD-based logic replacement applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCR3128XL-7TQG100I | 128 macrocells, same 7.5 ns speed grade and TQFP-100 package; lower logic density. | Suitable for smaller glue logic functions; insufficient for full 144-macrocell designs. | Select when design fits within 128 macrocells and cost optimization is prioritized. |
| XC95216-10TQG100I | 216 macrocells, 10 ns propagation delay, same voltage and package; higher density but slower timing. | Acceptable for less timing-critical control logic where additional macrocells are needed. | Choose when logic resource demand exceeds 144 macrocells and 10 ns delay is acceptable. |
Compared with XC95144XL-7TQG100I, the XCR3128XL-7TQG100I offers cost savings at reduced capacity, while the XC95216-10TQG100I trades speed for scalability - both require functional verification but share identical footprint and voltage requirements.
Availability
XC95144XL-7TQG100I is available at Aetrix Electronics and suitable for industrial control, test equipment, and legacy system upgrade programs requiring stable component supply over extended production lifecycles.
Supply support for XC95144XL-7TQG100I includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD acquired Xilinx in 2022, integrating its programmable logic portfolio including legacy XC9500XL CPLDs.
The XC9500XL family was designed for in-system programmable logic replacement in industrial, telecom, and computing applications where EEPROM-based non-volatility and JTAG accessibility were critical.
FAQ
What is the maximum operating frequency supported by the XC95144XL-7TQG100I?
The XC95144XL-7TQG100I has a 7.5 ns pin-to-pin propagation delay, supporting system clock frequencies up to 133 MHz in synchronous logic paths. Actual achievable frequency depends on internal routing, macrocell utilization, and external load conditions - verified timing analysis is required for critical paths in the XC95144XL-7TQG100I design.
Does the XC95144XL-7TQG100I support 5 V tolerant I/Os?
No, the XC95144XL-7TQG100I operates exclusively at 3.3 V and is not 5 V tolerant. All I/Os must be driven with 3.3 V logic levels; interfacing with 5 V systems requires level-shifting circuitry. This limitation is specified in the official XC95144XL-7TQG100I datasheet and applies across all temperature ranges.
Can the XC95144XL-7TQG100I be reprogrammed in the field without removing it from the PCB?
Yes, the XC95144XL-7TQG100I supports in-system programming (ISP) via its IEEE 1149.1 JTAG interface. Using standard JTAG adapters and Xilinx IMPACT or iMPACT-compatible tools, the XC95144XL-7TQG100I can be reconfigured in-circuit without physical removal or socketing.
What development software is required to program the XC95144XL-7TQG100I?
Xilinx ISE WebPACK (v14.7 or earlier) is the officially supported toolchain for synthesizing, fitting, and programming the XC95144XL-7TQG100I. Later versions of Vivado do not support this legacy CPLD family; the XC95144XL-7TQG100I requires ISE-specific HDL flows and JEDEC file generation.
Is the XC95144XL-7TQG100I RoHS compliant?
Yes, the XC95144XL-7TQG100I is RoHS compliant and lead-free, as confirmed by AMD's product change notices and packaging markings. The "G" in the suffix denotes green (halogen-free, Pb-free) packaging, consistent with EU RoHS Directive 2011/65/EU requirements for the XC95144XL-7TQG100I.
XC95144XL-7TQG100I Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- XC9500XL
- Package/Case:
- 100-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- In System Programmable (min 10K program/erase cycles)
- Delay Time tpd(1) Max:
- 7.5 ns
- Voltage Supply - Internal:
- 3V ~ 3.6V
- Number of Logic Elements/Blocks:
- 8
- Number of Macrocells:
- 144
- Number of Gates:
- 3200
- Number of I/O:
- 81
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TQFP (14x14)
XC95144XL-7TQG100I FAQ
1.How can I place an order for XC95144XL-7TQG100I through Aetrix?
Please submit a Request for Quotation (RFQ) for XC95144XL-7TQG100I on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC95144XL-7TQG100I reliable?
The price and inventory of XC95144XL-7TQG100I are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC95144XL-7TQG100I is usually 5 days.
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Once your XC95144XL-7TQG100I order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC95144XL-7TQG100I?
For technical support, including XC95144XL-7TQG100I datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC95144XL-7TQG100I requirements.
6.How does Aetrix verify that XC95144XL-7TQG100I is sourced from the original manufacturer or authorized distributors?
All XC95144XL-7TQG100I products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC95144XL-7TQG100I meets industry standards.
7.What is the process for return or replacement of XC95144XL-7TQG100I?
All XC95144XL-7TQG100I units undergo pre-shipment inspection (PSI). If there is an issue with XC95144XL-7TQG100I, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC95144XL-7TQG100I part is unused and in its original packaging.
Return procedure for XC95144XL-7TQG100I:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XC95144XL-7TQG100I Tags

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