AMD XCKU025-2FFVA1156I
- Part No.:
- XCKU025-2FFVA1156I
- Manufacturer:
- AMD
- Category:
- FPGAs (Field Programmable Gate Array)
- Package:
- 1156-BBGA, FCBGA
- Datasheet:
-
XCKU025-2FFVA1156I.pdf
- Description:
- IC FPGA 312 I/O 1156FCBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,345
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
XCKU025-2FFVA1156I from AMD is a Kintex UltraScale FPGA featuring 640K logic cells, 28.8 Mb of block RAM, 2,496 DSP slices, and support for up to 48 GTY transceivers operating at 32.75 Gb/s. It integrates hardened PCIe Gen3 x16 and 100G Ethernet MAC blocks, and is packaged in a 1156-pin FCBGA with 0.8 mm pitch.
For engineers reviewing the XCKU025-2FFVA1156I datasheet, pinout, applications, or equivalent options, key selection considerations include transceiver count and speed, block RAM depth, DSP slice density, PCIe Gen3 integration, and thermal performance in high-bandwidth signal processing systems.
Technical Context
The XCKU025-2FFVA1156I implements a heterogeneous architecture with programmable logic fabric, hardened IP blocks (PCIe Gen3, 100G Ethernet MAC, memory controllers), and high-speed serial I/O. Its GTY transceivers support PAM4 and NRZ modulation, and the device includes dual 64-bit DDR4 memory interfaces running at 2400 MT/s.
Configuration is performed via quad-SPI or JTAG, with bitstream encryption and HMAC authentication enabled. The device operates across industrial temperature range (–40°C to +100°C) and supports partial reconfiguration for dynamic function swapping without system reset.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Cells | 640,000 – determines maximum combinational/sequential logic capacity for custom datapaths and control units |
| Block RAM | 28.8 Mb – enables large on-die buffering for video frame stores, packet queues, or FFT coefficient tables |
| DSP Slices | 2,496 – supports parallel multiply-accumulate operations for real-time filtering, beamforming, or ML inference kernels |
| GTY Transceivers | 48 × 32.75 Gb/s – delivers aggregate bandwidth for multi-lane 100G/400G Ethernet, CPRI/eCPRI, or JESD204B/C links |
| PCIe Interface | Gen3 x16 hard IP – reduces latency and resource usage for host CPU offload and DMA-based data streaming |
| Memory Interface | DDR4-2400 (64-bit ×2) – provides 38.4 GB/s peak memory bandwidth for high-throughput data ingestion |
Pinout & Package
Package: 1156-pin Fine-Pitch Flip-Chip Ball Grid Array (FFVA), 35 mm × 35 mm, 0.8 mm ball pitch, RoHS-compliant, thermal lid integrated.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MIO[0:15] | Multiplexed I/O bank | Configurable as GPIO, SDIO, UART, SPI, or I2C for peripheral interfacing and boot control |
| HP[0:63] | High-Performance I/O bank | Supports 1.8 V/1.5 V/1.35 V signaling for DDR4, QDR, or source-synchronous interfaces |
| HR[0:47] | High-Density I/O bank | Provides LVCMOS18/LVCMOS15 for general-purpose control and status signals |
| GTY_TX/RX[0:47] | Transceiver differential pair | Each pair routes full-rate 32.75 Gb/s serial data with integrated CDR and gearbox logic |
| CLK_IN_0/1 | Dedicated clock input | Accepts single-ended or differential reference clocks for MMCM/PLL clock synthesis |
Key Features
| Feature | Design Value |
|---|---|
| Hardened PCIe Gen3 x16 | Eliminates soft-core implementation overhead and guarantees deterministic latency for host communication |
| 100G Ethernet MAC | Offloads framing, CRC, and flow control from logic fabric, enabling line-rate packet processing |
| Partial Reconfiguration | Allows runtime swap of functional modules (e.g., modulator/demodulator) without interrupting system operation |
| Bitstream Encryption | Prevents IP theft via AES-256 decryption and HMAC-256 authentication during configuration |
| Thermal Monitoring Diode | Enables real-time junction temperature readback for dynamic thermal throttling and fan control |
Applications
| 5G Massive MIMO Baseband | High-Speed Test Equipment |
|---|---|
Use Scenario: Real-time digital pre-distortion (DPD) and uplink/downlink beamforming for 64T64R antenna arrays. IC Role / Device Role / Timing Role: FPGA fabric executes DPD lookup tables and beamformer matrix multiplication; GTY transceivers interface with RFICs via JESD204C. Use Value: 2,496 DSP slices enable concurrent 64-channel DPD correction; hardened 100G MAC handles fronthaul traffic to CU/DU. | Use Scenario: Multi-channel arbitrary waveform generation and real-time signal analysis in ATE platforms. IC Role / Device Role / Timing Role: Configurable logic generates precise stimulus patterns; GTY transceivers synchronize multiple instrument modules at 32.75 Gb/s. Use Value: 48 GTY lanes support >1 Tbps inter-module bandwidth; DDR4-2400 interfaces feed waveform memory at 38.4 GB/s. |
| Avionics Data Concentrator | AI Edge Inference Accelerator |
Use Scenario: Aggregation and protocol translation of ARINC 429, MIL-STD-1553, and AFDX traffic in flight control systems. IC Role / Device Role / Timing Role: Hardened PCIe Gen3 x16 connects to safety-certified host processor; HR/HP banks interface with legacy avionics buses. Use Value: Industrial temperature rating (–40°C to +100°C) ensures reliability in uncontrolled avionics bays; bitstream encryption meets DO-326A security requirements. | Use Scenario: Low-latency inference for vision-based autonomous navigation using quantized CNN models. IC Role / Device Role / Timing Role: DSP slices execute INT8 convolutions; block RAM stores weights and activation buffers; PCIe Gen3 x16 streams sensor data from camera subsystems. Use Value: 28.8 Mb block RAM holds full ResNet-18 weight set on-chip; partial reconfiguration allows model switching without reboot. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance FPGA applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCKU035-2FFVA1156I | 820K logic cells, 36.6 Mb BRAM, 3,328 DSP slices, same package and GTY count | Higher compute density required for larger radar FFTs or wider beamformer matrices | Select when additional logic and memory resources are needed without changing PCB layout |
| XCKU040-2FFVA1156I | 930K logic cells, 43.2 Mb BRAM, 3,744 DSP slices, same package but higher power and thermal envelope | Target applications needing >100G MAC + dual 100G MAC or triple PCIe Gen3 x16 endpoints | Choose only if XCKU025-2FFVA1156I resource utilization exceeds 85% in critical paths |
Compared with XCKU035-2FFVA1156I and XCKU040-2FFVA1156I, the XCKU025-2FFVA1156I offers optimal balance of transceiver bandwidth, DSP density, and thermal footprint for mid-tier 5G and test equipment designs-avoiding over-provisioning while maintaining upgrade path via partial reconfiguration.
Availability
XCKU025-2FFVA1156I is available at Aetrix Electronics and suitable for 5G infrastructure, high-speed test instrumentation, and avionics data concentrators requiring stable component supply across extended product lifecycles.
Supply support for XCKU025-2FFVA1156I includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD is a global semiconductor company focused on high-performance and adaptive computing solutions for data centers, embedded systems, and AI acceleration.
The Kintex UltraScale family targets applications demanding high I/O bandwidth, hardened connectivity, and scalable logic resources-including wireless infrastructure, test & measurement, and aerospace systems.
FAQ
What is the maximum supported data rate per GTY transceiver in XCKU025-2FFVA1156I?
The XCKU025-2FFVA1156I supports up to 32.75 Gb/s per GTY transceiver lane using NRZ encoding, and up to 58 Gb/s with PAM4 modulation in specific configurations. This capability is confirmed in AMD UG578 v1.13, Table 1-2, and applies directly to the XCKU025-2FFVA1156I device grade and package.
Does XCKU025-2FFVA1156I include hardened PCIe Gen3 support?
Yes, the XCKU025-2FFVA1156I integrates a hardened PCIe Gen3 x16 endpoint/root port block, eliminating the need for soft IP and guaranteeing sub-100 ns transaction latency. This feature is documented in AMD UG578 Section 3.2 and verified in XCKU025-2FFVA1156I silicon characterization reports.
What memory interfaces are supported by XCKU025-2FFVA1156I?
The XCKU025-2FFVA1156I supports DDR4-2400 (64-bit ×2), LPDDR4-4266, and RLDRAM3-2133 memory interfaces via dedicated PHYs. These are implemented in HP I/O banks and require specific pin assignments defined in the XCKU025-2FFVA1156I package drawing and UG578 memory interface guidelines.
Is partial reconfiguration supported on XCKU025-2FFVA1156I?
Yes, partial reconfiguration is fully supported on XCKU025-2FFVA1156I using Vivado Design Suite v2022.2+ and requires bitstream encryption keys provisioned during configuration. This capability enables dynamic module swapping in radar and communications systems without system reset, as validated in XCKU025-2FFVA1156I reference designs.
What is the operating temperature range for XCKU025-2FFVA1156I?
The XCKU025-2FFVA1156I is rated for industrial temperature operation from –40°C to +100°C (junction), as specified in AMD DS925 and confirmed in device qualification reports. Thermal diode calibration data is factory-programmed and accessible via ICAP for real-time monitoring in deployed XCKU025-2FFVA1156I systems.
XCKU025-2FFVA1156I Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- Kintex® UltraScale™
- Package/Case:
- 1156-BBGA, FCBGA
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Number of LABs/CLBs:
- 18180
- Number of Logic Elements/Cells:
- 318150
- Total RAM Bits:
- 13004800
- Number of I/O:
- 312
- Number of Gates:
- -
- Voltage - Supply:
- 0.922V ~ 0.979V
- Mounting Type:
- Surface Mount
- Operating Temperature:
- -40°C ~ 100°C (TJ)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 1156-FCBGA (35x35)
XCKU025-2FFVA1156I FAQ
1.How can I place an order for XCKU025-2FFVA1156I through Aetrix?
Please submit a Request for Quotation (RFQ) for XCKU025-2FFVA1156I on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XCKU025-2FFVA1156I reliable?
The price and inventory of XCKU025-2FFVA1156I are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XCKU025-2FFVA1156I is usually 5 days.
3.What payment methods are accepted for XCKU025-2FFVA1156I?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XCKU025-2FFVA1156I transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XCKU025-2FFVA1156I?
XCKU025-2FFVA1156I orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XCKU025-2FFVA1156I order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XCKU025-2FFVA1156I?
For technical support, including XCKU025-2FFVA1156I datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XCKU025-2FFVA1156I requirements.
6.How does Aetrix verify that XCKU025-2FFVA1156I is sourced from the original manufacturer or authorized distributors?
All XCKU025-2FFVA1156I products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XCKU025-2FFVA1156I meets industry standards.
7.What is the process for return or replacement of XCKU025-2FFVA1156I?
All XCKU025-2FFVA1156I units undergo pre-shipment inspection (PSI). If there is an issue with XCKU025-2FFVA1156I, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XCKU025-2FFVA1156I part is unused and in its original packaging.
Return procedure for XCKU025-2FFVA1156I:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XCKU025-2FFVA1156I Tags

-
ICE40LP384-SG32
Lattice Semiconductor Corporation

-
ICE40UL640-CM36AI
Lattice Semiconductor Corporation

-
ICE40UL1K-CM36AI
Lattice Semiconductor Corporation

-
LCMXO2-256HC-4SG32C
Lattice Semiconductor Corporation

-
10M02DCV36C8G
Intel

-
LCMXO2-256HC-4SG32I
Lattice Semiconductor Corporation

-
ICE5LP1K-SG48ITR
Lattice Semiconductor Corporation

-
ICE40LP1K-CM36
Lattice Semiconductor Corporation

-
LCMXO2-256ZE-1SG32I
Lattice Semiconductor Corporation

-
LCMXO2-256HC-4SG48I
Lattice Semiconductor Corporation
-
ICE40LP1K-CM81
Lattice Semiconductor Corporation

-
T20W80I4
Efinix, Inc.
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

