AMD XCKU035-2FFVA1156I
- Part No.:
- XCKU035-2FFVA1156I
- Manufacturer:
- AMD
- Category:
- FPGAs (Field Programmable Gate Array)
- Package:
- 1156-BBGA, FCBGA
- Datasheet:
-
XCKU035-2FFVA1156I.pdf
- Description:
- IC FPGA 520 I/O 1156FCBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,363
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Product details
Overview
XCKU035-2FFVA1156I from AMD is a Kintex UltraScale FPGA featuring 352,000 logic cells, 24.8 Mb of block RAM, and 1,728 DSP slices. It supports PCIe Gen3 x8, 16.3 Gb/s transceivers, and operates at -2 speed grade with industrial temperature range (-40°C to +100°C). It is used in high-bandwidth data acquisition systems requiring deterministic latency and real-time processing.
For engineers reviewing the XCKU035-2FFVA1156I datasheet, pinout, applications, or equivalent options, key selection criteria include transceiver line rate, I/O bank voltage support, thermal envelope, and configuration interface compatibility with JTAG and SelectMAP.
Technical Context
The XCKU035-2FFVA1156I implements a heterogeneous architecture with programmable logic fabric, hardened IP blocks (PCIe Gen3, 10/25G Ethernet MAC), and multi-rate transceivers. It integrates dual 32-bit AXI HP slave interfaces and supports DDR4 memory interfaces up to 2400 MT/s.
Configuration is performed via quad-SPI flash or JTAG, with bitstream encryption enabled through AES-256 and HMAC authentication. The device uses 16nm FinFET process technology and supports partial reconfiguration for dynamic function swapping.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Cells | 352,000 - determines maximum combinational and sequential logic capacity for custom RTL implementation |
| Block RAM | 24.8 Mb - supports large on-die buffering, FIFOs, and lookup tables without external memory |
| DSP Slices | 1,728 - enables high-throughput fixed/floating-point math for radar, video, or AI inference acceleration |
| Transceiver Max Rate | 16.3 Gb/s - allows direct connection to 10G/25G Ethernet PHYs and CPRI/eCPRI interfaces |
| I/O Standards | LVCMOS, SSTL, HSTL, MIPI, LVDS - supports mixed-voltage board interfacing including DDR4 and sensor bridges |
| Speed Grade | -2 - guarantees timing closure at 1.0 GHz system clock with worst-case voltage/temperature margins |
| Operating Temp | -40°C to +100°C - qualified for industrial and outdoor embedded deployment without active cooling |
Pinout & Package
Package: 1156-pin Flip-Chip Fine-Pitch Ball Grid Array (FFVA) with 0.8 mm pitch, thermally enhanced with integrated heat slug. Compatible with standard reflow profiles and IPC-7351B footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MIO[0:15] | Multifunction I/O Bank 0 | Configurable as SDIO, UART, SPI, I2C, or GPIO; supports 1.8V/3.3V operation |
| HP[0:71] | High-Performance I/O Bank | Supports DDR4, PCIe, and transceiver reference clocks; 1.2V/1.35V/1.8V selectable |
| GTH[0:23] | Multi-gigabit Transceiver Pair | Each pair delivers 10–16.3 Gb/s serial links with built-in CDR and PRBS generation |
| CONFIG_IO | Configuration Interface | Dedicated pins for JTAG TCK/TMS/TDI/TDO and Quad-SPI flash boot signals |
| VCCINT/VCCAUX/VCCO | Power Supply Rails | Separate domains for core (0.85V), auxiliary (1.8V), and I/O (1.2–3.3V) enable low-noise partitioning |
Key Features
| Feature | Design Value |
|---|---|
| Hardened PCIe Gen3 x8 Endpoint | Reduces RTL integration effort and ensures compliance with PCIe 3.0 electrical and protocol layers |
| UltraScale+ Memory Controller | Provides native DDR4/LPDDR4 controller with ECC, 2400 MT/s data rate, and AXI4 interface |
| AES-256 Bitstream Encryption | Prevents reverse engineering and unauthorized cloning of FPGA configuration in field-deployed systems |
| Partial Reconfiguration Support | Enables runtime logic updates without system reset-critical for mission-critical telecom and defense applications |
| Integrated System Monitor | Delivers real-time die temperature, supply voltage, and current telemetry via I2C/JTAG interface |
Applications
| Radar Signal Processing | 5G Baseband Unit |
|---|---|
Use Scenario: Real-time beamforming and pulse-Doppler processing in phased-array radar systems. IC Role / Device Role / Timing Role: FPGA fabric executes time-critical FFT, CFAR, and STAP algorithms; transceivers interface with ADC/DACs at 2.4 GSPS. Use Value: Deterministic sub-100 ns latency and 16.3 Gb/s JESD204B link support enable coherent multi-channel RF sampling. | Use Scenario: Layer 1 PHY processing and fronthaul transport in massive MIMO 5G gNodeB units. IC Role / Device Role / Timing Role: Implements eCPRI over 25G Ethernet, CPRI mapping, and OFDM modulation/demodulation pipelines. Use Value: Hardened 25G Ethernet MAC and 16.3 Gb/s transceivers eliminate need for external SerDes, reducing BOM count and power. |
| Industrial Vision Inspection | High-Speed Data Acquisition |
Use Scenario: Sub-millisecond defect classification on production lines using multi-camera synchronized capture. IC Role / Device Role / Timing Role: Coordinates camera triggers, buffers image streams in block RAM, and runs CNN inference kernels on DSP slices. Use Value: 352K logic cells and 1,728 DSP slices deliver >128 GOPS INT8 throughput for edge AI vision at <5W typical power. | Use Scenario: Multi-channel oscilloscope and spectrum analyzer platforms capturing >1 GS/s per channel. IC Role / Device Role / Timing Role: Manages JESD204B lanes from 16-bit ADCs, performs real-time FFT and digital down-conversion. Use Value: 24.8 Mb on-chip RAM eliminates external DDR bottleneck, enabling zero-latency waveform reconstruction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance FPGA applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCKU040-2FFVA1156I | Higher logic density (408K LC), same package and pinout, +15% DSP slices | Better suited for complex 5G L1 stacks with dual-sector processing | Select when additional logic headroom is required without changing PCB layout |
| XCKU025-2FFVA1156I | Fewer logic cells (252K), reduced block RAM (16.1 Mb), same transceiver spec | Targeted at cost-sensitive radar front-ends with single-beam processing | Choose for lower-power, lower-cost deployments where full XCKU035 capacity is unused |
Compared with XCKU035-2FFVA1156I, the XCKU040 offers higher compute headroom within identical mechanical and thermal constraints, while the XCKU025 reduces cost and static power at the expense of algorithmic complexity and memory bandwidth.
Availability
XCKU035-2FFVA1156I is available at Aetrix Electronics and suitable for radar signal processing, 5G baseband units, and high-speed data acquisition requiring stable component supply across extended product lifecycles.
Supply support for XCKU035-2FFVA1156I includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD is a global semiconductor company delivering adaptive computing solutions for data center, embedded, and client markets with leadership in FPGA, CPU, and GPU technologies.
The Kintex UltraScale family targets high-performance, cost-optimized applications in wired communications, test & measurement, and aerospace systems where bandwidth, power efficiency, and reconfigurability are critical.
FAQ
What is the maximum supported DDR4 data rate for XCKU035-2FFVA1156I?
The XCKU035-2FFVA1156I supports DDR4 memory interfaces up to 2400 MT/s using its integrated UltraScale+ memory controller. This capability is verified in UG576 and applies directly to the XCKU035-2FFVA1156I with appropriate PCB layout and termination. The controller provides AXI4 interface, on-die termination, and ECC support for mission-critical applications.
Does XCKU035-2FFVA1156I support partial reconfiguration?
Yes, XCKU035-2FFVA1156I fully supports partial reconfiguration as defined in UG909. This feature allows dynamic logic module swapping during operation without resetting the entire device. XCKU035-2FFVA1156I leverages frame-based bitstream loading and hierarchical design flow to enable runtime adaptation in radar and telecom systems.
What transceiver protocols are natively supported by XCKU035-2FFVA1156I?
XCKU035-2FFVA1156I natively supports PCIe Gen3 x8, 10/25G Ethernet (via hardened MAC), CPRI, and JESD204B v1.1/v2.0 through its GTH transceivers and integrated IP blocks. These protocols are implemented in silicon and do not require external PHYs. All are validated for XCKU035-2FFVA1156I in production silicon.
Is XCKU035-2FFVA1156I qualified for industrial temperature operation?
Yes, XCKU035-2FFVA1156I is rated for industrial temperature range (-40°C to +100°C) and is tested per AMD's industrial qualification standards. This rating applies specifically to the -2 speed grade in FFVA1156 packaging and is documented in DS892. No derating is required within this range.
What configuration modes does XCKU035-2FFVA1156I support?
XCKU035-2FFVA1156I supports multiple configuration modes including JTAG, Quad-SPI flash, and SelectMAP. Configuration via Quad-SPI is the most common for production systems due to fast boot time and security features. All modes are electrically and functionally supported on the XCKU035-2FFVA1156I without hardware modification.
XCKU035-2FFVA1156I Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- Kintex® UltraScale™
- Package/Case:
- 1156-BBGA, FCBGA
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Number of LABs/CLBs:
- 25391
- Number of Logic Elements/Cells:
- 444343
- Total RAM Bits:
- 19456000
- Number of I/O:
- 520
- Number of Gates:
- -
- Voltage - Supply:
- 0.922V ~ 0.979V
- Mounting Type:
- Surface Mount
- Operating Temperature:
- -40°C ~ 100°C (TJ)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 1156-FCBGA (35x35)
XCKU035-2FFVA1156I FAQ
1.How can I place an order for XCKU035-2FFVA1156I through Aetrix?
Please submit a Request for Quotation (RFQ) for XCKU035-2FFVA1156I on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XCKU035-2FFVA1156I reliable?
The price and inventory of XCKU035-2FFVA1156I are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XCKU035-2FFVA1156I is usually 5 days.
3.What payment methods are accepted for XCKU035-2FFVA1156I?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XCKU035-2FFVA1156I transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XCKU035-2FFVA1156I?
XCKU035-2FFVA1156I orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XCKU035-2FFVA1156I order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XCKU035-2FFVA1156I?
For technical support, including XCKU035-2FFVA1156I datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XCKU035-2FFVA1156I requirements.
6.How does Aetrix verify that XCKU035-2FFVA1156I is sourced from the original manufacturer or authorized distributors?
All XCKU035-2FFVA1156I products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XCKU035-2FFVA1156I meets industry standards.
7.What is the process for return or replacement of XCKU035-2FFVA1156I?
All XCKU035-2FFVA1156I units undergo pre-shipment inspection (PSI). If there is an issue with XCKU035-2FFVA1156I, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XCKU035-2FFVA1156I part is unused and in its original packaging.
Return procedure for XCKU035-2FFVA1156I:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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