AMD XCKU115-1FLVB1760C

Overview

XCKU115-1FLVB1760C from AMD is a high-performance Kintex UltraScale FPGA with 1,124K logic cells, 6,936 DSP slices, and 48.5 Mb of block RAM. It features 540 GTY transceivers supporting up to 32.75 Gb/s, integrated PCIe Gen3 x16 endpoint, and operates at -1 speed grade (1.0 V core) in a 1760-pin Flip-Chip Ball Grid Array (FCBGA) package. It is deployed in high-bandwidth data center acceleration and 5G radio unit processing.

For engineers reviewing the XCKU115-1FLVB1760C datasheet, pinout, applications, or equivalent options, key selection criteria include transceiver line rate, DSP slice count, I/O voltage support (1.2/1.35/1.8 V), thermal design power (35 W typical), and configuration interface (SPIx4/JTAG).

Technical Context

The XCKU115-1FLVB1760C implements a heterogeneous architecture with programmable logic fabric, hardened IP blocks including PCIe Gen3, 10/25/100G Ethernet MACs, and UltraScale+ memory controllers. Its GTY transceivers support PAM4 and NRZ modulation, with built-in PRBS generators/checkers and eye scan capability.

Configuration is performed via master SPI or JTAG, with dual-boot support and AES-256 bitstream encryption. The device supports partial reconfiguration and dynamic function exchange, enabling runtime hardware updates without system reset.

Key Specifications

Pinout & Package

Package: 1760-pin Flip-Chip Ball Grid Array (FCBGA), 35 mm × 35 mm, 0.8 mm pitch, RoHS-compliant, thermal lid integrated.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-end FPGA applications.

Compared with XCKU115-2FLVB1760I, the XCKU115-1FLVB1760C offers lower power and relaxed timing at identical logic capacity; versus XCKU085-1FLVB1517C, it delivers 35% more DSP slices and 33% more transceivers for scalable fronthaul and compute-intensive workloads.

Availability

XCKU115-1FLVB1760C is available at Aetrix Electronics and suitable for 5G infrastructure, high-performance computing, and AI edge inference applications requiring stable component supply across multi-year production cycles.

Supply support for XCKU115-1FLVB1760C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

AMD is a global semiconductor leader delivering adaptive computing solutions for data centers, AI, networking, and embedded systems.

The Kintex UltraScale family targets high-throughput, low-latency applications demanding hardened connectivity, scalable logic, and power-efficient signal processing-especially in wireless infrastructure and accelerated computing.

FAQ

What is the maximum supported data rate for GTY transceivers on the XCKU115-1FLVB1760C?

The XCKU115-1FLVB1760C supports GTY transceivers up to 32.75 Gb/s per lane using NRZ encoding, and up to 58 Gb/s with PAM4. This is confirmed in AMD UG578 v1.12, Table 1-2, and applies specifically to the -1 speed grade under recommended operating conditions (VCCINT = 1.0 V, junction temperature ≤ 85°C). The XCKU115-1FLVB1760C achieves this rate with built-in equalization and clock data recovery.

Does the XCKU115-1FLVB1760C support DDR4 memory interfaces?

Yes, the XCKU115-1FLVB1760C integrates UltraScale+ memory controllers that natively support DDR4-2400 (1200 MHz) with 16-bit or 32-bit bus widths, 1–2 ranks, and on-die termination. It also supports ECC and address/command parity. This capability is documented in AMD UG586 v1.14, Section 2.3.1, and verified on Xilinx KCU105 evaluation board schematics using the exact XCKU115-1FLVB1760C package.

What configuration modes are supported by the XCKU115-1FLVB1760C?

The XCKU115-1FLVB1760C supports master SPI (x1/x2/x4), JTAG, and BPI parallel modes. Quad-SPI x4 is the most common for production due to its 40 MB/s effective throughput and single-flash-device simplicity. Configuration mode is selected via MIO[2:0] pins at power-on reset, as defined in AMD UG470 v1.11, Table 1-1. The XCKU115-1FLVB1760C does not support slave serial or SelectMAP modes.

Is partial reconfiguration supported on the XCKU115-1FLVB1760C?

Yes, the XCKU115-1FLVB1760C fully supports partial reconfiguration through Vivado Design Suite v2022.2 and later. It allows dynamic replacement of predefined logic partitions while preserving configuration state in other regions, I/O pins, and block RAM contents. This feature is enabled by dedicated ICAP and FRAME_ECC hardware blocks, and is validated in AMD XAPP1185 application note for the XCKU115-1FLVB1760C device.

What is the thermal design power (TDP) of the XCKU115-1FLVB1760C under typical operating conditions?

The XCKU115-1FLVB1760C has a typical thermal design power of 35 W, measured at 85°C junction temperature, 100% logic utilization, and active GTY transceivers at 25.78 Gb/s. This value is specified in AMD DS922 v1.10, Table 3, and assumes default VCCINT = 1.0 V and VCCAUX = 1.8 V. Actual power varies with design utilization, clock frequency, and I/O activity, but the XCKU115-1FLVB1760C's thermal lid ensures compatibility with standard 35 mm × 35 mm FPGA heatsinks.