AMD XCVU23P-1VSVA1365E
- Part No.:
- XCVU23P-1VSVA1365E
- Manufacturer:
- AMD
- Category:
- FPGAs (Field Programmable Gate Array)
- Package:
- 1365-BFBGA, FCBGA
- Datasheet:
-
XCVU23P-1VSVA1365E.pdf
- Description:
- IC FPGA VIRTEX-UP 1365FCBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,163
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
XCVU23P-1VSVA1365E from AMD is a high-performance Virtex UltraScale+ FPGA featuring 1,472K logic cells, 8,520 DSP slices, and 96.4 Mb of block RAM; it supports PCIe Gen4 x16, 25G transceivers, and operates at -1 speed grade in a 1365-pin flip-chip BGA package for high-end networking and radar signal processing.
For engineers reviewing the XCVU23P-1VSVA1365E datasheet, pinout, applications, or equivalent options, key selection factors include transceiver lane count and data rate, I/O voltage flexibility (1.8V/1.5V/1.35V/1.2V), thermal design power (TDP) of 55W, and support for DDR4-2400 memory interfaces.
Technical Context
The XCVU23P-1VSVA1365E implements a heterogeneous architecture with programmable logic, hardened IP blocks including PCIe Gen4 root port and endpoint controllers, and multi-rate transceivers capable of 25.78125 Gb/s operation. It integrates dual ARM Cortex-A53 processors for real-time control and system management.
Configuration is supported via quad-SPI, BPI, or JTAG; partial reconfiguration enables dynamic function swapping without full device reset. The device complies with IEEE 1149.1 and 1532 standards for boundary-scan and in-system programming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Cells | 1,472,000 - determines maximum combinational and sequential logic capacity for complex algorithm implementation |
| DSP Slices | 8,520 - enables parallel execution of high-throughput arithmetic operations such as FFTs and filtering |
| Block RAM | 96.4 Mb - provides on-chip memory for buffering, FIFOs, and lookup tables without external memory latency |
| Transceiver Max Rate | 25.78125 Gb/s - supports 25G Ethernet, CPRI, and JESD204B interface compliance |
| PCIe Interface | Gen4 x16 - delivers 32 GT/s per lane for high-bandwidth host interconnect in compute-accelerated systems |
| I/O Standards | LVDS, SSTL, HSTL, MIPI - enables direct interfacing with sensors, memory, and high-speed serial peripherals |
| TDP | 55 W - defines thermal envelope requiring active cooling and PCB copper pour planning |
Pinout & Package
Package: 1365-pin flip-chip BGA (VSVA1365), 35 mm × 35 mm, 0.8 mm pitch, RoHS-compliant, thermal lid integrated.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCCINT | Core supply rail | Supplies 0.85 V to FPGA fabric; requires low-noise regulation and local decoupling |
| VCCAUX | Auxiliary supply rail | Powers configuration logic, PCIe hard IP, and transceiver reference clocks at 1.8 V |
| MGTAVCC | Transceiver analog supply | Provides 0.95 V to high-speed SerDes analog circuitry; sensitive to ripple and noise |
| IO_Lx_y | Configurable I/O bank | Supports multiple voltage standards per bank; each bank has dedicated VCCO and VREF |
| CLK_IN_0_P/N | Differential clock input | Accepts 10–1250 MHz differential reference clocks for PLL/MMCM locking and timing closure |
| PROGRAM_B | Configuration reset | Active-low asynchronous reset that clears configuration memory and initiates reconfiguration sequence |
Key Features
| Feature | Design Value |
|---|---|
| Hardened PCIe Gen4 controller | Reduces RTL integration effort and ensures protocol compliance without soft-core overhead |
| 25G multi-rate transceivers | Enables single-lane interoperability across 10G/25G/50G PAM4 protocols with built-in PRBS generation/checking |
| ARM Cortex-A53 subsystem | Provides embedded Linux-capable processing for system boot, monitoring, and offload coordination |
| Partial reconfiguration support | Allows runtime logic module swapping-critical for adaptive radar waveform updates and protocol agility |
| UltraScale+ routing architecture | Delivers predictable timing convergence and reduced congestion in large hierarchical designs |
Applications
| Radar Signal Processing | 5G Massive MIMO Baseband |
|---|---|
Use Scenario: Real-time beamforming and pulse-Doppler processing in AESA radar systems. IC Role / Device Role / Timing Role: FPGA fabric executes time-critical FFTs and CFAR detection; transceivers interface with ADC/DAC arrays. Use Value: 25G transceivers enable direct connection to 12-bit 2.6 GSPS ADCs; 8,520 DSP slices sustain >100 GOPS sustained throughput. | Use Scenario: Digital pre-distortion (DPD) and uplink/downlink channel processing in 5G NR base stations. IC Role / Device Role / Timing Role: Configurable logic implements adaptive DPD algorithms; PCIe Gen4 x16 connects to host CPU for control plane traffic. Use Value: 1,472K logic cells accommodate concurrent wideband OFDM modulation and feedback loop correction logic. |
| High-Performance Computing Acceleration | Test & Measurement Equipment |
Use Scenario: Offloading matrix multiplication and sparse graph analytics in data center accelerators. IC Role / Device Role / Timing Role: Hardened PCIe Gen4 x16 serves as high-bandwidth host interface; block RAM buffers streaming tensor data. Use Value: 96.4 Mb block RAM eliminates need for external DDR4 in many inference kernels, reducing latency and power. | Use Scenario: Real-time protocol analysis and jitter tolerance testing in 25G/100G Ethernet test sets. IC Role / Device Role / Timing Role: Transceivers generate and analyze PRBS patterns; logic fabric implements state-machine-based packet inspection. Use Value: 25.78125 Gb/s transceiver rate matches IEEE 802.3by CAUI-4 specification for accurate physical-layer validation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-end FPGA applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCVU23P-2VSVA1365I | Higher speed grade (-2), 10% higher max frequency, 65W TDP | Better suited for timing-critical 25G+ line-rate packet processing | Select when design requires margin for worst-case process/voltage/temperature corners |
| XCVU19P-1VSVA1365E | Fewer logic cells (1,126K), 6,840 DSP slices, same package and transceiver capability | Lower cost option for mid-tier 5G RU and radar sub-systems | Choose when application fits within reduced resource budget and maintains identical board footprint |
Compared with XCVU23P-1VSVA1365E, the -2 speed grade offers tighter timing closure at higher frequencies but increases thermal load, while the XCVU19P-1VSVA1365E retains pin compatibility and transceiver performance at lower logic density-enabling scalable platform design across performance tiers.
Availability
XCVU23P-1VSVA1365E is available at Aetrix Electronics and suitable for radar signal processing, 5G baseband acceleration, and high-performance computing applications requiring stable component supply and long-term industrial availability.
Supply support for XCVU23P-1VSVA1365E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD is a global semiconductor company designing adaptive computing platforms for data centers, AI, embedded systems, and high-performance applications.
The Virtex UltraScale+ family targets mission-critical infrastructure where deterministic latency, high transceiver bandwidth, and hardware-software co-design are essential-especially in defense radar, 5G infrastructure, and accelerated computing.
FAQ
What is the maximum transceiver data rate supported by XCVU23P-1VSVA1365E?
The XCVU23P-1VSVA1365E supports a maximum transceiver data rate of 25.78125 Gb/s per lane. This enables compliance with 25G Ethernet, CPRI Option 8, and JESD204B/C standards. All 64 transceiver quads on the XCVU23P-1VSVA1365E are rated for this speed under standard operating conditions.
Does XCVU23P-1VSVA1365E include a hard processor system?
Yes, the XCVU23P-1VSVA1365E integrates a dual-core ARM Cortex-A53 processor subsystem running at up to 1.5 GHz. This hard processor system supports boot-from-Flash, Linux OS execution, and real-time firmware coordination with programmable logic-without consuming fabric resources.
What configuration modes are supported by XCVU23P-1VSVA1365E?
The XCVU23P-1VSVA1365E supports multiple configuration modes including master/slave SPI, BPI, and JTAG. Quad-SPI mode allows fast parallel loading from external flash; JTAG is used for debugging and boundary-scan verification. Configuration bitstream can be encrypted using AES-256 keys.
Is XCVU23P-1VSVA1365E pin-compatible with other Virtex UltraScale+ devices?
The XCVU23P-1VSVA1365E uses the VSVA1365 package and shares mechanical footprint with XCVU19P-1VSVA1365E and XCVU23P-2VSVA1365I. However, I/O banking and voltage assignments differ between variants-requiring schematic and constraint file review before substitution.
What is the block RAM capacity of XCVU23P-1VSVA1365E?
The XCVU23P-1VSVA1365E provides 96.4 Mb of total block RAM distributed across 2,160 BRAM primitives. Each BRAM can be configured as 36 Kb dual-port memory or 18 Kb single-port, supporting true dual-port read/write with independent clocks for pipelined dataflow architectures.
XCVU23P-1VSVA1365E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- Virtex® UltraScale+™
- Package/Case:
- 1365-BFBGA, FCBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Number of LABs/CLBs:
- 128700
- Number of Logic Elements/Cells:
- 2252250
- Total RAM Bits:
- 77909197
- Number of I/O:
- 364
- Number of Gates:
- -
- Voltage - Supply:
- 0.825V ~ 0.876V
- Mounting Type:
- Surface Mount
- Operating Temperature:
- 0°C ~ 100°C (TJ)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 1365-FCBGA (35x35)
XCVU23P-1VSVA1365E FAQ
1.How can I place an order for XCVU23P-1VSVA1365E through Aetrix?
Please submit a Request for Quotation (RFQ) for XCVU23P-1VSVA1365E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XCVU23P-1VSVA1365E reliable?
The price and inventory of XCVU23P-1VSVA1365E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XCVU23P-1VSVA1365E is usually 5 days.
3.What payment methods are accepted for XCVU23P-1VSVA1365E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XCVU23P-1VSVA1365E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XCVU23P-1VSVA1365E?
XCVU23P-1VSVA1365E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XCVU23P-1VSVA1365E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XCVU23P-1VSVA1365E?
For technical support, including XCVU23P-1VSVA1365E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XCVU23P-1VSVA1365E requirements.
6.How does Aetrix verify that XCVU23P-1VSVA1365E is sourced from the original manufacturer or authorized distributors?
All XCVU23P-1VSVA1365E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XCVU23P-1VSVA1365E meets industry standards.
7.What is the process for return or replacement of XCVU23P-1VSVA1365E?
All XCVU23P-1VSVA1365E units undergo pre-shipment inspection (PSI). If there is an issue with XCVU23P-1VSVA1365E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XCVU23P-1VSVA1365E part is unused and in its original packaging.
Return procedure for XCVU23P-1VSVA1365E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XCVU23P-1VSVA1365E Tags

-
ICE40LP384-SG32
Lattice Semiconductor Corporation

-
ICE40UL640-CM36AI
Lattice Semiconductor Corporation

-
ICE40UL1K-CM36AI
Lattice Semiconductor Corporation

-
LCMXO2-256HC-4SG32C
Lattice Semiconductor Corporation

-
10M02DCV36C8G
Intel

-
LCMXO2-256HC-4SG32I
Lattice Semiconductor Corporation

-
ICE5LP1K-SG48ITR
Lattice Semiconductor Corporation

-
ICE40LP1K-CM36
Lattice Semiconductor Corporation

-
LCMXO2-256ZE-1SG32I
Lattice Semiconductor Corporation

-
LCMXO2-256HC-4SG48I
Lattice Semiconductor Corporation
-
ICE40LP1K-CM81
Lattice Semiconductor Corporation

-
T20W80I4
Efinix, Inc.
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
