My Inquiry
My Account
AMD XCVU23P-3VSVA1365E
- Part No.:
- XCVU23P-3VSVA1365E
- Manufacturer:
- AMD
- Category:
- FPGAs (Field Programmable Gate Array)
- Package:
- 1365-BFBGA, FCBGA
- Datasheet:
-
XCVU23P-3VSVA1365E.pdf
- Description:
- IC FPGA VIRTEX-UP 1365FCBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,278
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
XCVU23P-3VSVA1365E from AMD is a high-performance Virtex UltraScale+ FPGA featuring 1,472K logic cells, 8,520 DSP slices, and 96.4 Mb of block RAM; supports PCIe Gen4 x16, 25G transceivers, and DDR4 memory interfaces; deployed in AI acceleration and high-throughput data center compute platforms.
For engineers reviewing the XCVU23P-3VSVA1365E datasheet, pinout, applications, or equivalent options, key selection factors include transceiver line rate (25.78125 Gbps), I/O voltage support (0.35–1.8 V), thermal design power (145 W), and package pin count (1365).
Technical Context
The XCVU23P-3VSVA1365E implements a heterogeneous architecture with programmable logic fabric, hardened IP blocks for PCIe Gen4, Ethernet MACs, and memory controllers, and multi-rate transceivers supporting protocols including CPRI, JESD204B/C, and OTN. It integrates UltraScale+ SelectIO technology with SSTL, HSTL, LVCMOS, and differential standards.
Configuration is performed via quad-SPI, BPI, or JTAG; partial reconfiguration is supported. The device uses 16nm FinFET process technology and includes integrated system monitoring (temperature, voltage, current) with on-die sensors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Cells | 1,472,000 - total configurable LUT/FF pairs for complex digital logic implementation |
| DSP Slices | 8,520 - fixed-point and floating-point arithmetic units with 27×18 multiplier and 48-bit accumulator |
| Block RAM | 96.4 Mb - distributed as 36 Kb BRAM primitives for on-chip data buffering and FIFOs |
| Transceiver Line Rate | 25.78125 Gbps - supports 25G Ethernet, PCIe Gen4, and JESD204C without gearbox |
| I/O Standards | SSTL-15/18, HSTL-I/II, LVCMOS 1.2/1.5/1.8/2.5/3.3 V - enables direct interface to DDR4, LPDDR4, and legacy memory |
| Thermal Design Power | 145 W - defines heatsink and airflow requirements for sustained operation at speed grade -3 |
| Package | 1365-pin Flip-Chip BGA (VSVA1365) - 35 mm × 35 mm body, 0.8 mm pitch, RoHS-compliant |
Pinout & Package
The XCVU23P-3VSVA1365E is housed in a 1365-pin flip-chip ball grid array (FCBGA) package designated VSVA1365, with 35 mm × 35 mm footprint, 0.8 mm ball pitch, and thermal lid for enhanced heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCCINT | Core supply rail | Supplies 0.85 V ±3% to programmable logic and CLB fabric; requires low-noise regulation |
| VCCAUX | Auxiliary supply rail | Provides 1.8 V ±3% to configuration logic, PCIe hard IP, and clock management tiles |
| VCCO | I/O bank supply | Bank-specific voltage (0.35–1.8 V) sets I/O signaling standard and drive strength |
| MGTAVCC | Transceiver analog supply | 1.0 V ±2% analog supply for GTY transceiver PLLs and serializers/deserializers |
| CONFIG_IO | Configuration I/O | Dedicated pins for mode selection, INIT_B, PROGRAM_B, and configuration clock input |
| CLK_IN | Primary clock input | Dedicated differential input for main system clock feeding MMCM/PLL clock networks |
Key Features
| Feature | Design Value |
|---|---|
| Heterogeneous integration | Combines programmable logic, hardened PCIe Gen4, 100G Ethernet MAC, and DDR4 controller in single die |
| Partial reconfiguration | Enables dynamic logic swapping without full device reset-critical for runtime adaptation in AI inference pipelines |
| UltraScale+ SelectIO | Supports 32 I/O standards across 36 banks with per-bank voltage control and slew rate tuning |
| GTY transceivers | 25.78125 Gbps line rate with built-in PRBS generation/checking, eye scan, and adaptive equalization |
| System monitoring | On-die temperature sensor (±2°C accuracy), supply monitors, and current estimation for thermal-aware scheduling |
Applications
| AI Accelerator Card | Data Center SmartNIC |
|---|---|
Use Scenario: High-bandwidth inference engine for LLM token generation with real-time latency constraints. IC Role / Device Role / Timing Role: Primary compute fabric executing custom quantized kernels and managing PCIe Gen4 host interface and HBM2E memory coherency. Use Value: 1,472K logic cells and 8,520 DSP slices enable concurrent execution of multiple transformer layers; 25G transceivers feed HBM2E stacks at peak bandwidth. | Use Scenario: Programmable network offload engine handling TLS termination, packet filtering, and RDMA acceleration. IC Role / Device Role / Timing Role: Real-time packet processing unit interfacing with 100G Ethernet PHYs and host CPU via PCIe Gen4 x16. Use Value: Hardened 100G Ethernet MAC and PCIe Gen4 controller reduce latency vs. software-based NICs; 96.4 Mb BRAM buffers bursty traffic flows. |
| Radar Signal Processor | 5G Massive MIMO Baseband Unit |
Use Scenario: Multi-channel FMCW radar baseband processing in automotive ADAS with strict deterministic timing. IC Role / Device Role / Timing Role: Real-time FFT, CFAR detection, and beamforming engine synchronized to 100 MHz reference clock with sub-nanosecond jitter tolerance. Use Value: Low-jitter clocking infrastructure and deterministic routing enable <10 ns timing closure across 1,000+ parallel channels. | Use Scenario: Digital pre-distortion (DPD) and uplink/downlink channel processing for 64T64R active antenna systems. IC Role / Device Role / Timing Role: JESD204C interface controller and real-time DPD coefficient update engine operating at 245.76 MSPS sample rate. Use Value: GTY transceivers support JESD204C subclass 1 with deterministic latency; 27×18 DSP slices execute 4th-order polynomial DPD in under 200 ns. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-end FPGA compute applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCVU23P-2VSVA1365I | Lower speed grade (-2 vs. -3); 12% lower max transceiver rate (24.33 Gbps); 13% lower TDP (126 W) | Suitable for cost-sensitive AI training accelerators where 25G line rate is not required | Select when thermal budget is constrained and PCIe Gen4 x16 bandwidth is sufficient without 25G Ethernet |
| XCVU28P-3VSVA1365E | Higher logic density (1,889K cells), +2,100 DSP slices, +12.8 Mb BRAM; identical package and speed grade | Used in next-gen 400G SmartNICs requiring larger on-die buffer and higher arithmetic throughput | Choose when additional logic capacity and DSP resources are needed without changing PCB layout |
Compared with XCVU23P-2VSVA1365I and XCVU28P-3VSVA1365E, the XCVU23P-3VSVA1365E delivers optimal balance of 25G transceiver performance, logic capacity, and thermal envelope for AI inference and 100G networking-without over-provisioning resources or exceeding board-level cooling limits.
Availability
XCVU23P-3VSVA1365E is available at Aetrix Electronics and suitable for AI accelerator cards, data center SmartNICs, and 5G baseband units requiring stable component supply across multi-year production cycles.
Supply support for XCVU23P-3VSVA1365E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD is a global semiconductor company delivering adaptive computing solutions for data centers, AI, embedded, and client markets through FPGA, adaptive SoC, and GPU technologies.
The Virtex UltraScale+ family targets high-performance compute and signal processing applications demanding hardened connectivity, massive on-die memory, and deterministic low-latency execution-especially in AI inference, 5G infrastructure, and advanced radar systems.
FAQ
What is the maximum transceiver line rate supported by the XCVU23P-3VSVA1365E?
The XCVU23P-3VSVA1365E supports a maximum transceiver line rate of 25.78125 Gbps using its GTY transceivers. This enables native compliance with 25G Ethernet, PCIe Gen4, and JESD204C protocols without gearbox logic. The XCVU23P-3VSVA1365E achieves this rate across all 64 transceiver quads in the device when operating within thermal and voltage specifications.
Does the XCVU23P-3VSVA1365E support partial reconfiguration?
Yes, the XCVU23P-3VSVA1365E fully supports partial reconfiguration through Vivado Design Suite tools. This allows dynamic swapping of logic modules while the rest of the design remains operational-essential for adaptive workloads like AI model switching or protocol stack updates. The XCVU23P-3VSVA1365E implements dedicated configuration logic and frame-based bitstream loading to ensure safe, deterministic reconfiguration.
What I/O standards does the XCVU23P-3VSVA1365E support?
The XCVU23P-3VSVA1365E supports 32 I/O standards including SSTL-15/18, HSTL-I/II, LVCMOS (1.2 V to 3.3 V), and differential standards such as LVDS, BLVDS, and TMDS. Each of its 36 I/O banks operates independently with configurable VCCO, enabling mixed-voltage interfaces-for example, DDR4 memory (1.2 V) alongside legacy peripherals (3.3 V). The XCVU23P-3VSVA1365E's SelectIO architecture ensures signal integrity across all supported standards.
What is the thermal design power (TDP) of the XCVU23P-3VSVA1365E?
The XCVU23P-3VSVA1365E has a thermal design power of 145 W at speed grade -3 under worst-case operating conditions. This value guides heatsink sizing, airflow requirements, and PCB thermal vias placement. The XCVU23P-3VSVA1365E includes on-die temperature sensors and supply monitors to enable real-time thermal throttling and power-aware scheduling in production systems.
Is the XCVU23P-3VSVA1365E pin-compatible with other Virtex UltraScale+ devices in the VSVA1365 package?
The XCVU23P-3VSVA1365E shares the same 1365-pin VSVA1365 package footprint with XCVU28P-3VSVA1365E and XCVU19P-3VSVA1365E, but pin functions are not fully interchangeable due to differences in transceiver count, I/O bank allocation, and hardened IP placement. While mechanical mounting is identical, PCB layout reuse requires verification of signal mapping and power delivery against each device's specific pinout documentation. The XCVU23P-3VSVA1365E must be validated independently for each target application.
XCVU23P-3VSVA1365E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- Virtex® UltraScale+™
- Package/Case:
- 1365-BFBGA, FCBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Number of LABs/CLBs:
- 128700
- Number of Logic Elements/Cells:
- 2252250
- Total RAM Bits:
- 77909197
- Number of I/O:
- 364
- Number of Gates:
- -
- Voltage - Supply:
- 0.873V ~ 0.927V
- Mounting Type:
- Surface Mount
- Operating Temperature:
- 0°C ~ 100°C (TJ)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 1365-FCBGA (35x35)
XCVU23P-3VSVA1365E FAQ
1.How can I place an order for XCVU23P-3VSVA1365E through Aetrix?
Please submit a Request for Quotation (RFQ) for XCVU23P-3VSVA1365E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XCVU23P-3VSVA1365E reliable?
The price and inventory of XCVU23P-3VSVA1365E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XCVU23P-3VSVA1365E is usually 5 days.
3.What payment methods are accepted for XCVU23P-3VSVA1365E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XCVU23P-3VSVA1365E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XCVU23P-3VSVA1365E?
XCVU23P-3VSVA1365E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XCVU23P-3VSVA1365E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XCVU23P-3VSVA1365E?
For technical support, including XCVU23P-3VSVA1365E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XCVU23P-3VSVA1365E requirements.
6.How does Aetrix verify that XCVU23P-3VSVA1365E is sourced from the original manufacturer or authorized distributors?
All XCVU23P-3VSVA1365E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XCVU23P-3VSVA1365E meets industry standards.
7.What is the process for return or replacement of XCVU23P-3VSVA1365E?
All XCVU23P-3VSVA1365E units undergo pre-shipment inspection (PSI). If there is an issue with XCVU23P-3VSVA1365E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XCVU23P-3VSVA1365E part is unused and in its original packaging.
Return procedure for XCVU23P-3VSVA1365E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XCVU23P-3VSVA1365E Tags
-
ICE40LP384-SG32
Lattice Semiconductor Corporation
-
ICE40UL640-CM36AI
Lattice Semiconductor Corporation
-
ICE40UL1K-CM36AI
Lattice Semiconductor Corporation
-
LCMXO2-256HC-4SG32C
Lattice Semiconductor Corporation
-
10M02DCV36C8G
Intel
-
LCMXO2-256HC-4SG32I
Lattice Semiconductor Corporation
-
ICE5LP1K-SG48ITR
Lattice Semiconductor Corporation
-
ICE40LP1K-CM36
Lattice Semiconductor Corporation
-
LCMXO2-256ZE-1SG32I
Lattice Semiconductor Corporation
-
LCMXO2-256HC-4SG48I
Lattice Semiconductor Corporation
-
ICE40LP1K-CM81
Lattice Semiconductor Corporation
-
T20W80I4
Efinix, Inc.
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
