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Texas Instruments XRM48L952PGET
- Part No.:
- XRM48L952PGET
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
XRM48L952PGET.pdf
- Description:
- IC MCU 16/32BIT 3MB FLSH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:3,181
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Product details
Overview
XRM48L952PGET from Texas Instruments is a safety-certified 32-bit ARM Cortex-R4F microcontroller for functional safety-critical systems, featuring dual lockstep CPUs, 3 MB flash with ECC, 256 KB RAM with ECC, and real-time peripherals including two N2HET timers and dual 12-bit ADCs (24-channel total). It operates at up to 220 MHz with 1.2 V core and 3.3 V I/O supply, targeting industrial PLCs, medical infusion pumps, and turbine control.
For engineers reviewing the XRM48L952PGET datasheet, XRM48L952PGET pinout, XRM48L952PGET application, or XRM48L952PGET equivalent, this page delivers verified technical context, package-specific pin mapping, safety architecture details, and validated alternative options - all grounded in TI's SPNS177D production datasheet and PGE package documentation.
Technical Context
The XRM48L952PGET implements a dual-CPU lockstep architecture with BIST, ECC on flash and SRAM, parity-protected peripheral memories, and dedicated Error Signaling Module (ESM) with external ERROR pin. Its FMPLL generates internal clocks up to 220 MHz, while the Global Clock Module (GCM) routes seven clock sources across domains.
It integrates two Next Generation High-End Timer (N2HET) modules - N2HET1 (32 channels) and N2HET2 (18 channels) - each with hardware angle generator, HTU DMA engine, and MPU-protected memory access. The device supports IEEE 802.3-compliant 10/100 Mbps Ethernet MAC with MII/RMII/MDIO, three DCAN controllers (CAN 2.0B), and dual USB (2-port host + 1-device).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-R4F, 220 MHz max, 1.66 DMIPS/MHz - enables deterministic real-time execution for ASIL-D–capable safety firmware. |
| Memory | 3 MB program flash + 64 KB emulated EEPROM (both with ECC); 256 KB data RAM with ECC - ensures integrity of code and runtime variables in harsh environments. |
| Analog Peripherals | Dual 12-bit MibADCs: ADC1 (24 channels), ADC2 (16 shared), 64-word parity-protected buffers - supports redundant sensor acquisition in safety loops. |
| Timing & Control | N2HET1 (32 channels), N2HET2 (18 channels), RTI timer, 96-channel VIM - provides precise PWM, capture, and GPIO timing for actuator/sensor interfacing without CPU load. |
| Communication | 3× DCAN (1 Mbps), 3× MibSPI, 2× SPI, 2× SCI/LIN, I²C, EMAC (MII/RMII), USB 2.0 host/device - meets multi-bus redundancy requirements in industrial networks. |
| Safety Features | Dual lockstep CPUs, CPU/RAM BIST, ESM with ERROR pin, voltage/clock monitoring, memory protection unit (MPU) - satisfies ISO 26262 ASIL-D and IEC 61508 SIL-3 certification pathways. |
| Supply Voltages | VCC = 1.14–1.32 V (core), VCCIO = 3.0–3.6 V (I/O), VCCAD = 3.0–5.25 V (ADC) - enables robust operation across extended industrial temperature range (–40°C to 105°C). |
Pinout & Package
LQFP-144 (PGE) package, 20.0 mm × 20.0 mm body size, green RoHS-compliant finish. Pin functions defined per TI SPNS177D Section 4.1 and Table 4-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| nPORRST | Power-On Reset Input | Asynchronous active-low reset asserted during power ramp; initiates full system initialization and safety checks. |
| nERROR | Error Signaling Output | Open-drain output driven low by ESM upon detected fault (e.g., ECC double-bit error, clock failure) - connects to external watchdog or system shutdown logic. |
| GIOA[0]–GIOA[7], GIOB[0]–GIOB[7] | General-Purpose I/O | 16 configurable GPIO pins with interrupt capability; default multiplexed functions include CAN, LIN, SPI, and ADC inputs. |
| MIBSPI1_CLK / SOMI / SIMO / nCS[0–3] | MibSPI1 Interface | Primary high-speed serial interface supporting up to 6 chip selects; used for sensor hubs, FPGA configuration, or isolated communication peripherals. |
| AD1IN[0]–AD1IN[23], AD2IN[0]–AD2IN[15] | Analog Input Channels | 24 dedicated + 16 shared ADC input pins; support simultaneous sampling groups and hardware-triggered sequences for time-critical diagnostics. |
| N2HET1[0]–N2HET1[31], N2HET2[0]–N2HET2[17] | N2HET Timer I/O | 50 programmable high-resolution timer pins (32+18) - configured as PWM outputs, capture inputs, or GPIO with sub-microsecond timing resolution. |
| EMIF_ADDR[0–21], DATA[0–15], nCS[0,2–4], nWE, nRAS, nCAS | External Memory Interface | 16-bit parallel bus supporting SDRAM, NOR/NAND flash, or FPGA glue logic - enables off-chip data logging or firmware update storage. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Lockstep Cortex-R4F CPUs | Hardware-enforced instruction-level comparison detects transient faults; triggers ESM response within one cycle - foundational for ASIL-D compliance. |
| ECC on Flash & RAM | Single-bit correction / double-bit detection on all program and data memory - prevents silent data corruption in long-life safety systems. |
| Two N2HET Coprocessors | Offloads complex timing tasks (e.g., motor commutation, valve sequencing) from main CPU; HTU enables zero-CPU DMA transfers to/from timer RAM. |
| Integrated Safety Monitor | Error Signaling Module (ESM) aggregates 100+ internal fault sources (clock, voltage, memory, peripheral) and asserts nERROR or interrupt - eliminates need for external safety monitor IC. |
| Multi-Protocol Communication | Three independent CAN controllers + Ethernet + USB + LIN/SCI - supports layered network architectures (e.g., CAN for fieldbus, Ethernet for HMI, USB for service port) in single-chip designs. |
| Debug & Trace Support | ETM-R4 instruction trace, RTP for RAM/peripheral access tracing, DMM for runtime memory injection - enables certified toolchain integration for DO-178C/IEC 62304 validation. |
Applications
| Industrial PLC Safety Logic | Medical Infusion Pump Control |
|---|---|
Use Scenario: Safe programmable logic controller executing SIL-3 logic for emergency stop, motion control, and interlock monitoring in factory automation. IC Role / Device Role / Timing Role: Primary safety controller running certified runtime with lockstep CPU verification, ECC memory, and dual-channel ADC for redundant position feedback. Use Value: Eliminates need for external safety monitor IC; reduces BOM count and PCB area while meeting IEC 61508 Part 2 Annex F requirements for hardware fault tolerance. |
Use Scenario: Precision fluid delivery system requiring fail-safe motor control, pressure sensing, and dose verification in critical care environments. IC Role / Device Role / Timing Role: Real-time safety MCU managing stepper motor N2HET PWM, dual ADC sampling of flow/pressure sensors, and USB host for calibration data upload. Use Value: Integrated ESM and ERROR pin enable immediate pump shutdown on memory or clock fault - directly supports FDA 510(k) Class II device safety justification. |
| Wind Turbine Pitch Control | Radiation Therapy Beam Gate |
Use Scenario: Redundant pitch actuation system adjusting blade angle based on wind speed, vibration, and grid conditions in offshore turbines. IC Role / Device Role / Timing Role: Dual-core safety processor executing pitch algorithm with N2HET-driven servo control, CAN-based sensor fusion, and EMAC for SCADA telemetry. Use Value: 220 MHz performance and 3 MB flash allow complex model-predictive control algorithms with full safety stack - extends turbine uptime under IEC 61400-25 cybersecurity constraints. |
Use Scenario: Beam collimation system requiring microsecond-accurate gate timing synchronized to radiation pulse and patient imaging data. IC Role / Device Role / Timing Role: Deterministic timing controller using N2HET1 for beam shutter actuation and RTI timer for interlock latency measurement. Use Value: Sub-100 ns N2HET timing resolution and hardware angle generator ensure beam-on accuracy within ±0.1° - satisfies IEC 62304 Class C software safety requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar safety microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| RM48L952ZWT | Same die, 337-ball NFBGA (16 mm × 16 mm); higher pin count enables full EMIF, additional CAN/USB signals, and more GPIO. | Preferred for space-constrained designs needing maximum peripheral routing flexibility and thermal dissipation via solder balls. | Select ZWT when board layout requires fine-pitch BGA routing, higher I/O density, or enhanced thermal performance over QFP. |
| RM48L750PGE | Lower-spec variant: 2 MB flash, 192 KB RAM, no EMIF, single USB host port, 200 MHz max clock - identical PGE package and pinout. | Suitable for cost-sensitive safety applications with reduced memory and interface needs (e.g., basic motor drives). | Choose RM48L750PGE only if application fits within smaller memory footprint and omits Ethernet/EMIF requirements - avoids overdesign. |
Compared with RM48L952ZWT, XRM48L952PGET offers identical safety architecture and core peripherals in a more manufacturable LQFP package but sacrifices EMIF and some CAN/USB signal routing flexibility; versus RM48L750PGE, it delivers 50% more flash, full USB/Ethernet support, and higher clock headroom for complex safety stacks.
Availability
XRM48L952PGET is available at Aetrix Electronics and suitable for industrial safety PLCs, medical infusion pumps, and wind turbine pitch control systems requiring stable component supply, long-term lifecycle assurance, and certified functional safety compliance.
Supply support for XRM48L952PGET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with deep expertise in functional safety silicon and automotive/industrial qualification.
The RM48L952 product line is part of TI's Hercules™ safety MCUs, designed specifically for ASIL-B/D and SIL-2/3 applications where hardware-level fault detection, memory integrity, and deterministic real-time control are mandatory.
FAQ
What safety certifications does the XRM48L952PGET support?
The XRM48L952PGET is architected to support ISO 26262 ASIL-D and IEC 61508 SIL-3 certification. Its dual lockstep CPUs, ECC memory, BIST, ESM, and voltage/clock monitors provide the hardware foundation required for certification. TI supplies safety manuals, FMEDA reports, and diagnostic software libraries - but final certification is performed by the end-system integrator per their specific application context and toolchain.
Does the XRM48L952PGET include an integrated Ethernet PHY?
No, the XRM48L952PGET includes only the Ethernet Media Access Controller (EMAC) - a MAC-layer IP block compliant with IEEE 802.3. It requires an external PHY chip (e.g., DP83848) connected via MII or RMII interface. The device supports MDIO for PHY register access and auto-negotiation control, but does not integrate physical layer transceivers.
Can the XRM48L952PGET's N2HET modules drive stepper motors directly?
The N2HET modules in the XRM48L952PGET generate precise PWM and timing waveforms but lack integrated power drivers. They can directly control external stepper motor driver ICs (e.g., DRV88xx series) via STEP/DIR or PWM inputs. Each N2HET channel supports sub-microsecond resolution, enabling microstepping control up to 256x with hardware-generated phase timing - reducing CPU overhead in motion control loops.
What is the role of the 64 KB emulated EEPROM in the XRM48L952PGET?
The XRM48L952PGET uses 64 KB of its 3 MB flash memory to emulate EEPROM functionality - providing nonvolatile storage for calibration data, device configuration, or event logs with wear leveling and ECC protection. Unlike true EEPROM, it requires software-managed erase/write cycles, but TI's HALCoGen drivers abstract this complexity and guarantee 100K write cycles with built-in error recovery.
How does the XRM48L952PGET handle ADC synchronization across its two MibADC modules?
The XRM48L952PGET supports hardware-synchronized conversion between MibADC1 and MibADC2 using the AD1EVT and AD2EVT trigger signals. A single external event (e.g., timer overflow or GPIO edge) can initiate simultaneous sampling on both ADCs - critical for phase-current measurement in motor control or differential sensor pairs in medical devices. This synchronization occurs within ±1 ADC clock cycle, ensuring coherent multi-channel acquisition.
XRM48L952PGET Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 144-LQFP
- Series:
- Hercules™ RM4 ARM® Cortex®-R4
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-R4F
- Core Size:
- 16/32-Bit
- Speed:
- 220MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MibSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, POR, PWM, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.14V ~ 1.32V
- Data Converters:
- A/D 24x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
XRM48L952PGET FAQ
1.How can I place an order for XRM48L952PGET through Aetrix?
Please submit a Request for Quotation (RFQ) for XRM48L952PGET on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XRM48L952PGET reliable?
The price and inventory of XRM48L952PGET are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XRM48L952PGET is usually 5 days.
3.What payment methods are accepted for XRM48L952PGET?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XRM48L952PGET transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XRM48L952PGET?
XRM48L952PGET orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XRM48L952PGET order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XRM48L952PGET?
For technical support, including XRM48L952PGET datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XRM48L952PGET requirements.
6.How does Aetrix verify that XRM48L952PGET is sourced from the original manufacturer or authorized distributors?
All XRM48L952PGET products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XRM48L952PGET meets industry standards.
7.What is the process for return or replacement of XRM48L952PGET?
All XRM48L952PGET units undergo pre-shipment inspection (PSI). If there is an issue with XRM48L952PGET, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XRM48L952PGET part is unused and in its original packaging.
Return procedure for XRM48L952PGET:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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