STMicroelectronics 74AC373MTR

Overview

74AC373MTR from STMicroelectronics is a high-speed CMOS octal D-type transparent latch with 3-state non-inverting outputs, designed for bus-oriented applications requiring bidirectional data flow control. It features 5 ns typical propagation delay at 5 V, ±24 mA output drive, 2 V to 6 V operating voltage range, and pin/function compatibility with standard 74-series 373 latches. Used in microprocessor address/data bus latching and memory interface circuits.

For engineers reviewing the 74AC373MTR datasheet, 74AC373MTR pinout, 74AC373MTR application, or 74AC373MTR equivalent, key selection criteria include latch enable timing (tPLH/tPHL ≈ 5–10.5 ns), 3-state output disable time (tPHZ ≤ 10 ns), symmetrical drive strength (|IOH| = IOL ≥ 24 mA), and wide supply tolerance (2–6 V) enabling mixed-voltage system interfacing.

Technical Context

The 74AC373 implements an edge-transparent latch architecture controlled by LE (latch enable): when LE is HIGH, Q outputs follow D inputs; when LE transitions LOW, outputs hold the last D value. OE (output enable) independently controls 3-state output drivers, allowing high-impedance tri-state operation without affecting internal latch state.

All eight D/Q channels operate synchronously under shared LE/OE control. Input thresholds are rail-proportional (VIH/VIL = 70%/30% of VCC), ensuring robust noise immunity (≥28% VCC) across the full 2–6 V supply range and temperature span (–55°C to +125°C).

Key Specifications

Pinout & Package

74AC373MTR is supplied in a 20-pin SOIC (Small Outline Integrated Circuit) package, 7.9 mm × 13.0 mm body, 1.27 mm pitch, RoHS-compliant, surface-mountable.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal D-type latch applications.

Compared with 74ACT373MTR, the 74AC373MTR offers significantly lower quiescent current (4 µA vs 80 µA) for power-sensitive designs, while matching propagation delay and drive strength; versus SN74AC373N, it delivers identical functionality in a space-saving SOIC package optimized for automated SMT production.

Availability

74AC373MTR is available at Aetrix Electronics and suitable for microprocessor bus interfaces, memory address latching, industrial I/O expansion, and digital signal routing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AC373MTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management ICs with strong analog and mixed-signal design heritage.

The 74AC logic family was developed to deliver high-speed CMOS performance with TTL-compatible drive and noise immunity, targeting legacy system upgrades and mixed-voltage industrial control applications.

FAQ

What is the maximum operating frequency supported by the 74AC373MTR?

The 74AC373MTR does not specify a maximum clock frequency, as it is a transparent latch-not a clocked flip-flop. Its usable data rate depends on propagation delay (tPD ≤ 10.5 ns at 5 V) and minimum pulse width (tW ≥ 4.5 ns). In practice, it reliably supports bus handshaking up to ~50 MHz in well-terminated systems with proper setup/hold timing.

Can OE and LE be tied together for simplified control?

Yes, OE and LE may be connected if only latching (not 3-state control) is needed-but this forfeits independent output disabling. When tied, both functions activate simultaneously: LE = LOW latches data and OE = LOW enables outputs. For true 3-state operation during latched hold, OE must remain LOW while LE returns HIGH after capture.

Does the 74AC373MTR support mixed-voltage operation between 3.3 V and 5 V domains?

Yes-its 2 V to 6 V VCC range and rail-proportional input thresholds (VIH = 70% VCC, VIL = 30% VCC) allow direct interfacing: a 3.3 V system can drive its inputs when VCC = 5 V (VIH = 3.5 V min), and its outputs swing rail-to-rail, meeting 3.3 V input requirements when loaded appropriately.

Is there a version with inverted outputs?

No-the 74AC373MTR has strictly non-inverting outputs. For inverted output functionality, STMicroelectronics offers the 74AC374MTR (octal D flip-flop, non-inverting) and 74AC573MTR (octal latch, non-inverting); the inverted-output counterpart is the 74AC574MTR (octal D flip-flop, non-inverting), not a latch. No AC-series inverted-output octal latch exists in ST's portfolio.