Nexperia USA Inc. 74AUP1G373GW,125

Overview

74AUP1G373GW,125 from Nexperia is a single-channel low-power D-type transparent latch with 3-state output, Schmitt-trigger inputs, and IOFF partial power-down capability. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC, supports -40 °C to +125 °C, and enables data latching in battery-powered sensor interfaces and portable logic subsystems.

For engineers reviewing the 74AUP1G373GW,125 datasheet, 74AUP1G373GW,125 pinout, 74AUP1G373GW,125 application, or 74AUP1G373GW,125 equivalent, key selection criteria include its ultra-low static current, overvoltage-tolerant 3.6 V inputs, sub-1 ns propagation delay at 3.3 V, IOFF-enabled system-level power sequencing, and TSSOP6 (SOT363-2) package compatibility with high-density PCB layouts.

Technical Context

This device implements a single D-latch with active-HIGH latch enable (LE) and active-LOW output enable (OE), enabling transparent data pass-through when LE is HIGH and holding the last valid D value when LE transitions LOW. Its Schmitt-trigger inputs tolerate slow-rising signals and reject noise up to ±100 mV hysteresis margin.

The IOFF circuit disables outputs and blocks backflow current when VCC = 0 V, supporting hot-insertion and multi-rail partial power-down. Input overvoltage tolerance to 3.6 V allows interfacing with higher-voltage domains without level shifters, while CPD = 2.8 pF ensures minimal dynamic switching power at 3.3 V/1 MHz.

Key Specifications

Pinout & Package

74AUP1G373GW,125 uses the SOT363-2 (TSSOP6) package: plastic thin shrink small outline, 6 leads, 1.25 mm body width, 0.65 mm pitch, and exposed pad not present. Pin 1 is marked by a lower-left corner indicator below the "aW" marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type transparent latch applications.

Compared with SN74LVC1G373DBVR and 74LVC1G74GW,125, the 74AUP1G373GW,125 uniquely combines sub-μA static current, IOFF protection, and 3-state output - making it optimal for ultra-low-power, multi-rail, and shared-bus designs where leakage control and signal integrity are critical.

Availability

74AUP1G373GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and IoT edge node data aggregation requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G373GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained systems, emphasizing nanowatt static power, wide-VCC operation, and robust IO specifications for next-generation portable and automotive electronics.

FAQ

What is the minimum supply voltage for reliable operation of the 74AUP1G373GW,125?

The device is fully specified down to 0.8 V VCC, with guaranteed functionality including Schmitt-trigger hysteresis, IOFF behavior, and 3-state control. At 0.8 V, propagation delay increases to ~21 ns (CL = 5 pF), but static current remains ≤0.5 μA - ideal for energy-harvesting or coin-cell applications where voltage droop occurs.

How does the IOFF feature protect the device during partial power-down?

When VCC = 0 V, the IOFF circuit actively disables both input and output buffers, limiting leakage current to ±0.75 μA regardless of voltage applied to D, Q, LE, or OE pins. This prevents reverse current flow that could damage upstream drivers or destabilize powered-down rails in mixed-supply systems.

Can the 74AUP1G373GW,125 interface directly with 5 V logic outputs?

No - while inputs tolerate up to +4.6 V absolute maximum, the recommended operating input voltage is limited to 3.6 V. Applying sustained 5 V signals risks long-term reliability degradation. For 5 V interfacing, use a series resistor + clamping diode or a dedicated level translator such as the NXH010P120MNF.

What is the significance of the Schmitt-trigger input on the LE and D pins?

Schmitt-trigger action provides ≥100 mV hysteresis between rising and falling thresholds, allowing clean latching even with slow-rising signals (e.g., RC-filtered switch inputs or long PCB traces). This eliminates need for external debounce circuitry and prevents metastability during marginal transitions.