NXP Semiconductors 74AHC373D,112

Overview

74AHC373D,112 from Nexperia is an octal D-type transparent latch with 3-state outputs, used for data latching and bus isolation in digital logic systems. It features independent latch enable (LE, active HIGH) and output enable (OE, active LOW), operates from 2.0 V to 5.5 V, supports -40 °C to +125 °C ambient range, and provides overvoltage-tolerant inputs up to 5.5 V - enabling mixed-voltage interfacing in microcontroller I/O expansion and memory address/data buffering.

For engineers reviewing the 74AHC373D,112 datasheet, 74AHC373D,112 pinout, 74AHC373D,112 application, or 74AHC373D,112 equivalent, key selection criteria include propagation delay (≤9.0 ns at VCC = 4.5–5.5 V, CL = 15 pF), 3-state output disable timing (tdis ≤11.5 ns), latch set-up/hold times (tsu = th = 4.0 ns), and SO20 package compatibility with legacy 74-series PCB footprints.

Technical Context

The 74AHC373D implements eight independent D-type latches with transparent mode when LE is HIGH and edge-triggered capture on HIGH-to-LOW LE transition. Each latch output connects to a common 3-state buffer controlled solely by OE - enabling full bus contention avoidance without affecting internal latch states.

Its CMOS AHC-family architecture delivers balanced tPHL/tPLH propagation delays, Schmitt-trigger inputs for noise immunity, and input overvoltage tolerance beyond VCC - allowing safe interfacing between 3.3 V logic driving 5 V buses or vice versa, without level-shifting circuitry.

Key Specifications

Pinout & Package

74AHC373D,112 is housed in a plastic small outline package (SO20, SOT163-1) with 20 leads and 7.5 mm body width - compatible with standard SOIC-20 footprint and reflow soldering profiles.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with 74AHC373PW,118, the 74AHC373D,112 offers lower thermal resistance (12.3 mW/K derating above 109 °C vs. 10.0 mW/K above 100 °C) and proven manufacturability in SO20 wave-solder processes; versus SN74AHCT373N, it adds 2.0 V operation and 5.5 V input tolerance - enabling broader system-level voltage flexibility.

Availability

74AHC373D,112 is available at Aetrix Electronics and suitable for microcontroller I/O expansion, memory address latching, and industrial bus isolation requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AHC373D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer applications.

The 74AHC373 belongs to Nexperia's advanced high-speed CMOS (AHC) logic family - engineered for low-power, high-noise-immunity digital interfacing in resource-constrained embedded systems operating across wide voltage and temperature ranges.

FAQ

What is the maximum clock frequency supported by the 74AHC373D,112?

The 74AHC373D,112 does not operate on a clock signal - it is an edge-triggered transparent latch controlled by the LE input. Its usable data rate is determined by propagation delay (≤9.0 ns) and set-up/hold timing (4.0 ns/1.0 ns), supporting reliable operation in bus systems with cycle times ≥25 ns (i.e., up to 40 MHz effective throughput).

Can the 74AHC373D,112 be used to interface 3.3 V microcontrollers with 5 V peripherals?

Yes - its inputs tolerate up to 5.5 V regardless of VCC, and it operates down to 2.0 V. When powered at 3.3 V, it safely accepts 5 V signals on Dn and LE/OE pins, and outputs 3.3 V logic levels compatible with 5 V-tolerant peripherals, eliminating external level shifters in many cases.

Is the 74AHC373D,112 pin-compatible with older 74LS373 devices?

Yes - the SO20 pinout (SOT163-1) matches industry-standard 74-series 20-pin layouts: Q0–Q7, D0–D7, OE, LE, GND, and VCC occupy identical positions. However, electrical behavior differs: AHC uses CMOS inputs (no DC loading), requires no pull-ups, and has faster timing than bipolar LS logic.

Does the 74AHC373D,112 require external pull-up or pull-down resistors on control inputs?

No - all inputs feature Schmitt-trigger action with defined thresholds and sufficient noise margin. OE and LE may be driven directly from CMOS logic outputs. Pull resistors are unnecessary unless implementing failsafe default states (e.g., 10 kΩ pull-down on OE to ensure outputs remain disabled at power-up).