Nexperia USA Inc. 74AHC373D,118

Overview

74AHC373D,118 from Nexperia is an octal D-type transparent latch with 3-state outputs, used for data latching and bus isolation in digital systems. It features independent latch enable (LE, active HIGH) and output enable (OE, active LOW), operates from 2.0 V to 5.5 V, supports -40 °C to +125 °C, and offers overvoltage-tolerant inputs up to 5.5 V for mixed-voltage interfacing.

For engineers reviewing the 74AHC373D,118 datasheet, 74AHC373D,118 pinout, 74AHC373D,118 application, or 74AHC373D,118 equivalent, key selection criteria include propagation delay (≤9.0 ns at 5 V/15 pF), 3-state output control timing (enable/disable ≤13.0 ns), latch transparency behavior, and SO20 package compatibility with legacy 74-series board layouts.

Technical Context

The device implements eight independent D-type latches with synchronous transparency: when LE is HIGH, Qn follows Dn in real time; when LE transitions LOW, the input state is captured and held. OE operates independently-asserting OE HIGH places all eight outputs in high-impedance mode without affecting latch state.

Inputs feature Schmitt-trigger action for noise immunity and accept voltages up to 5.5 V regardless of VCC (2.0–5.5 V), enabling level translation between 3.3 V logic driving 5 V buses or interfacing with higher-voltage peripherals. Latch operation is fully static and compatible with CMOS/TTL input thresholds across its full voltage and temperature range.

Key Specifications

Pinout & Package

74AHC373D,118 is housed in a plastic small outline package (SO20, SOT163-1) with 20 leads and 7.5 mm body width, optimized for surface-mount assembly and thermal performance up to 125 °C ambient.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with 74AHC373PW,118, the SO20 variant offers easier manual prototyping and legacy footprint compatibility; versus SN74AHCT373N, it provides superior mixed-voltage interoperability but requires careful attention to input voltage levels in TTL-only systems.

Availability

74AHC373D,118 is available at Aetrix Electronics and suitable for industrial control systems, automotive body electronics, and legacy computing hardware requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AHC373D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices with leadership in efficiency, miniaturization, and reliability for high-volume applications.

The 74AHC series targets general-purpose logic applications demanding low power, wide voltage operation, and robust noise immunity - designed specifically for industrial, computing, and communications infrastructure where signal integrity and thermal resilience are critical.

FAQ

Can 74AHC373D,118 operate with VCC = 2.5 V while interfacing with 5 V inputs?

Yes. Its inputs are overvoltage tolerant up to 5.5 V regardless of VCC, so it can safely accept 5 V signals while powered from 2.5 V. Output VOH will be ~2.3 V (min) at 4 mA load, sufficient to drive other 2.5 V logic inputs with margin.

What is the maximum clock frequency supported for transparent mode operation?

The device has no internal clock; maximum effective rate depends on propagation delay and set-up/hold timing. With tpd ≤9.0 ns and tsu/th = 4.0 ns/1.0 ns at 5 V, it supports reliable data capture up to ~80 MHz in transparent mode when LE is held HIGH and D inputs meet timing constraints.

Is there a risk of bus contention when multiple 74AHC373D,118 devices share the same data lines?

No, if OE is properly controlled. All outputs enter high-impedance when OE = HIGH, eliminating contention. Ensure OE is asserted HIGH on all but one device during any bus transaction, and verify that OE transition timing meets tdis ≤13.0 ns to prevent glitches.

Does 74AHC373D,118 require external pull-up or pull-down resistors on OE or LE?

Not inherently - both OE and LE are CMOS inputs with <0.1 μA leakage. However, in systems with floating control lines during power-up or reset, weak pull-downs (e.g., 100 kΩ) on OE prevent unintended output activation, and pull-downs on LE avoid spurious latching during initialization.