Nexperia USA Inc. 74AHC373PW,112

Overview

74AHC373PW,112 from Nexperia is an octal D-type transparent latch with 3-state outputs, used for data latching and bus isolation in digital systems. It operates across 2.0–5.5 V supply, features overvoltage-tolerant inputs up to 5.5 V, supports -40 °C to +125 °C operation, and delivers propagation delays as low as 4.0 ns (VCC = 4.5–5.5 V, CL = 15 pF). It is commonly deployed in microcontroller address/data bus buffering and legacy parallel interface isolation.

For engineers reviewing the 74AHC373PW,112 datasheet, 74AHC373PW,112 pinout, 74AHC373PW,112 application, or 74AHC373PW,112 equivalent, key selection considerations include latch enable (LE) timing behavior, 3-state output control via OE, input overvoltage tolerance enabling mixed-voltage interfacing, and TSSOP20 package thermal derating above 100 °C.

Technical Context

The device implements eight independent D-type latches with synchronous transparent operation: when LE is HIGH, Qn follows Dn in real time; when LE transitions LOW, the input state is captured and held. The 3-state outputs are controlled solely by OE (active LOW), independent of latch state - enabling bus sharing without disturbing stored data.

Inputs feature Schmitt-trigger action for noise immunity and accept voltages up to 5.5 V regardless of VCC, allowing level translation between 3.3 V and 5 V domains. Latch set-up time is 4.0 ns and hold time is 1.0 ns at VCC = 4.5–5.5 V, ensuring reliable capture in high-speed digital interfaces.

Key Specifications

Pinout & Package

TSSOP20 plastic thin shrink small outline package (SOT360-1), 20-pin, body width 4.4 mm, lead pitch 0.65 mm, rated for 100 °C ambient before linear derating (10.0 mW/K).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with 74AHC373PW,112, the SO20 variant offers easier manual handling but lower power density, while the AHCT version trades AHC's wide VCC range for guaranteed TTL-level input recognition - making each alternative optimal only under specific board-level interface constraints.

Availability

74AHC373PW,112 is available at Aetrix Electronics and suitable for microcontroller bus buffering, legacy parallel interface isolation, industrial PLC I/O expansion, and test equipment signal conditioning requiring stable component supply across extended temperature ranges.

Supply support for 74AHC373PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AHC373 belongs to Nexperia's advanced high-speed CMOS logic family, designed specifically for low-power, high-noise-immunity digital interfacing in space-constrained industrial and embedded systems.

FAQ

Can 74AHC373PW,112 operate reliably with VCC = 2.3 V?

Yes. The device is fully specified from 2.0 V to 5.5 V. At VCC = 2.3 V, VIH is guaranteed ≥1.5 V and VOL ≤0.5 V (IO = 4.0 mA), supporting interoperability with 2.5 V logic families. Propagation delay increases to ~13.5 ns (CL = 15 pF), which remains suitable for sub-50 MHz bus applications.

What happens to the latch state when OE is HIGH?

The latch state remains unchanged when OE is HIGH. Only the output drivers enter high-impedance mode; internal storage retains the last captured D-input values. This allows safe bus sharing - multiple 74AHC373PW,112 devices can share a common data bus with only one enabled at a time.

Is the TSSOP20 package RoHS-compliant and lead-free?

Yes. The 74AHC373PW,112 in SOT360-1 (TSSOP20) packaging is RoHS-compliant and lead-free per EU Directive 2011/65/EU, with homogeneous lead content < 0.1 wt%. The package uses matte tin (Sn) termination and meets JEDEC J-STD-020 moisture sensitivity level 1 (MSL1) for unlimited floor life at ≤30 °C/60% RH.

How does input overvoltage tolerance work without external clamping?

The inputs integrate internal diode clamps to VCC and GND, rated for continuous 5.5 V input even when VCC = 2.0 V. Current into these clamps is limited by series resistance and process design, ensuring no damage occurs within the absolute maximum rating of ±20 mA - eliminating need for external Schottky diodes in most mixed-voltage designs.