Nexperia USA Inc. 74ALVC373D,112

Overview

74ALVC373D,112 from Nexperia is an octal D-type transparent latch with 3-state outputs, used for data latching and bus isolation in digital systems. It operates from 1.65 V to 3.6 V, features latch enable (LE) and output enable (OE) controls, supports -40 °C to +125 °C operation, and includes IOFF circuitry for partial power-down protection in mixed-voltage designs.

For engineers reviewing the 74ALVC373D,112 datasheet, 74ALVC373D,112 pinout, 74ALVC373D,112 application, or 74ALVC373D,112 equivalent, key selection criteria include its 20-pin SO20 package, Schmitt-trigger input tolerance, 3.3 ns max propagation delay at 3.3 V, IOFF-enabled power-down safety, and compatibility with TTL-level inputs in 1.65–3.6 V supply domains.

Technical Context

This device implements eight independent D-type latches with shared LE and OE controls. Each latch enters transparent mode when LE is HIGH (output follows D-input), and holds data on LE's HIGH-to-LOW transition. OE independently places all outputs in high-impedance state without affecting latch contents.

Schmitt-trigger inputs ensure robustness against slow signal edges, while the IOFF circuit disables outputs during VCC = 0 V, preventing backflow current. The design complies with JEDEC standards JESD8-7, JESD8-5, and JESD8C/JESD36 across its full voltage range.

Key Specifications

Pinout & Package

74ALVC373D,112 is housed in a plastic small outline package (SO20, SOT163-1) with 20 leads and 7.5 mm body width. Pin 1 is OE (active LOW), pin 11 is LE (active HIGH), pins 3/4/7/8/13/14/17/18 are D0–D7 inputs, pins 2/5/6/9/12/15/16/19 are Q0–Q7 3-state outputs, pin 10 is GND, and pin 20 is VCC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with SN74LVC373APWR and 74LVC373PW,118, the 74ALVC373D,112 offers SO20 mechanical compatibility, proven thermal performance in legacy industrial designs, and identical IOFF behavior-making it optimal for retrofitting or volume production where board layout and qualification stability are critical.

Availability

74ALVC373D,112 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, memory address latching, and automated test fixture control requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74ALVC373D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74ALVC373 belongs to Nexperia's advanced low-voltage CMOS logic family, designed specifically for robust, low-power data latching in mixed-supply systems with stringent power-down safety requirements.

FAQ

What is the minimum recommended supply voltage for reliable operation of 74ALVC373D,112?

The device is fully specified from 1.65 V to 3.6 V per JEDEC JESD8-7. At 1.65 V, VIH is guaranteed ≥ 0.65 × VCC (≥ 1.07 V), and VOL remains ≤ 0.3 V with 6 mA load. Operation below 1.65 V is not characterized and may result in undefined logic states or increased static current.

Can 74ALVC373D,112 safely interface with 5 V TTL outputs?

Yes - its inputs tolerate up to 3.6 V regardless of VCC level, and VIH is defined down to 0.65 × VCC. When VCC = 3.3 V, VIH ≥ 2.0 V ensures reliable recognition of 5 V TTL HIGH levels (2.4–5 V), while the Schmitt trigger prevents metastability on slow transitions.

How does the IOFF feature behave during system power sequencing?

When VCC drops to 0 V, the IOFF circuit automatically disables all outputs, limiting OFF-state leakage to ±10 μA maximum. This prevents reverse current flow from powered downstream buses into the unpowered latch, protecting both the device and connected circuitry during staggered power-up/down sequences.

Is the 74ALVC373D,112 pin-compatible with older 74HC373 or 74LS373 devices?

No - while functionally similar, the 74ALVC373D,112 uses different input thresholds, output drive strength, and IOFF architecture. Its pinout matches standard 20-pin SO latches (OE, D0–D7, Q0–Q7, LE, VCC, GND), but electrical behavior differs significantly: HC/LS parts lack IOFF, have higher VCC minima (2 V/4.75 V), and do not support 1.65 V operation.