Nexperia USA Inc. 74ALVC373PW,112
- Part No.:
- 74ALVC373PW,112
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Latches
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74ALVC373PW,112.pdf
- Description:
- IC D-TYPE TRANSP SGL 8:8 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,032
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Product details
Overview
74ALVC373PW,112 from Nexperia is an octal D-type transparent latch with 3-state outputs, used for data latching and bus isolation in digital logic systems. It operates from 1.65 V to 3.6 V, features latch enable (LE) and output enable (OE) controls, supports -40 °C to +125 °C operation, and includes IOFF circuitry for partial power-down protection in mixed-voltage systems.
For engineers reviewing the 74ALVC373PW,112 datasheet, 74ALVC373PW,112 pinout, 74ALVC373PW,112 application, or 74ALVC373PW,112 equivalent, key selection criteria include 3-state bus driving capability, Schmitt-trigger input tolerance for slow-edge signals, IOFF-enabled power-down isolation, and TSSOP20 package compatibility with high-density PCB layouts.
Technical Context
The device implements eight independent D-type latches with transparent mode when LE is HIGH and edge-triggered capture on LE HIGH-to-LOW transition. Each latch output drives a 3-state buffer controlled separately by OE (active LOW), enabling bidirectional bus control without affecting internal latch states.
Schmitt-trigger inputs ensure robust noise immunity against slow-rising/falling signals, while the IOFF circuit disables outputs and blocks backflow current when VCC = 0 V - critical for hot-swap and partial-power-down architectures in industrial and embedded controllers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 3.6 V - enables direct interface with 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Propagation Delay (D→Q) | 1.0 ns (min) to 3.8 ns (max) at VCC = 3.0–3.6 V - supports >260 MHz data throughput in transparent mode. |
| IOFF Leakage Current | ±10 μA max at VCC = 0 V - prevents damaging backflow current during system power sequencing. |
| Input Voltage Tolerance | Inputs tolerant to 3.6 V regardless of VCC - allows safe interfacing with higher-voltage peripherals. |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor drives. |
| ESD Protection | HBM >2000 V, CDM >1000 V - meets JEDEC JS-001/JS-002 for robust handling in automated assembly lines. |
| Power Dissipation Capacitance | CPD = 35 pF (outputs active), 14 pF (3-state) - enables accurate dynamic power estimation in battery-powered designs. |
Pinout & Package
TSSOP20 package (SOT360-1): 4.4 mm body width, 0.65 mm pitch, 20-terminal surface-mount plastic thin shrink small outline package optimized for thermal performance and board space efficiency.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable | Active-LOW control: asserts high-impedance state on all Q outputs independently of latch state. |
| 2 (Q0), 5 (Q1), 6 (Q2), 9 (Q3), 12 (Q4), 15 (Q5), 16 (Q6), 19 (Q7) | 3-State Latch Outputs | Drive bidirectional data buses; tri-state when OE = HIGH, reflect stored D-input when OE = LOW and LE = LOW. |
| 3 (D0), 4 (D1), 7 (D2), 8 (D3), 13 (D4), 14 (D5), 17 (D6), 18 (D7) | Data Inputs | Accept 1.65–3.6 V logic levels; Schmitt-triggered for noise immunity on slow-rising control/data lines. |
| 11 (LE) | Latch Enable | Active-HIGH: enables transparent mode; HIGH-to-LOW edge captures D-inputs into latches. |
| 10 (GND) | Ground Reference | 0 V reference for all I/O and internal logic; must be low-impedance for stable timing and noise rejection. |
| 20 (VCC) | Supply Voltage | Primary power rail; powers internal logic and output drivers; requires local 100 nF decoupling per device. |
Key Features
| Feature | Design Value |
|---|---|
| IOFF Partial Power-Down | Disables outputs and blocks backflow current when VCC = 0 V - essential for hot-plug and multi-rail power sequencing. |
| Schmitt-Trigger Inputs | Input hysteresis ≥0.3 V at VCC = 3.3 V - eliminates chatter on noisy or slow-switching control lines like reset or enable signals. |
| Overvoltage-Tolerant Inputs | Withstand up to 3.6 V regardless of VCC setting - enables safe connection to 3.3 V peripherals even when operating at 1.8 V. |
| Latch Transparency Control | LE-driven dual-mode operation: real-time pass-through (LE = HIGH) or static storage (LE = LOW) - simplifies synchronous data capture in microcontroller interfaces. |
| JEDEC Compliance | Fully compliant with JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), and JESD8C/JESD36 (2.7–3.6 V) - guarantees interoperability across voltage-tiered logic families. |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
Use Scenario: Isolating microcontroller GPIOs from high-current solenoid drivers and sensor inputs in programmable logic controller racks. IC Role / Device Role / Timing Role: Acts as a buffered, latched interface between 3.3 V MCU and 5 V/12 V field-side circuits, with OE synchronized to scan cycle boundaries. Use Value: Prevents bus contention during firmware updates and enables deterministic I/O state retention during MCU reset sequences. | Use Scenario: Managing door lock actuator status feedback and window motor control signals in centralized body electronics units. IC Role / Device Role / Timing Role: Latches door position sensor data during CAN message transmission windows and isolates MCU pins from ESD-prone harness connections via 3-state outputs. Use Value: Eliminates need for discrete pull-up/pull-down networks and reduces EMC susceptibility through controlled output slew rates and IOFF protection. |
| Test Equipment Digital Pattern Generator | Medical Infusion Pump Controller |
Use Scenario: Generating precise, glitch-free stimulus patterns for IC functional testing using FPGA-controlled parallel data streams. IC Role / Device Role / Timing Role: Captures parallel pattern words from FPGA fabric on LE edge and holds them stable for DUT stimulus while OE gates output transitions to avoid metastability. Use Value: Enables sub-4 ns setup/hold margins and eliminates pattern corruption due to clock skew between FPGA and DUT interfaces. | Use Scenario: Buffering and latching flow rate calibration data and motor phase commands in safety-critical infusion pump mainboards. IC Role / Device Role / Timing Role: Stores calibrated DAC settings during power-up sequencing and provides fault-isolated outputs to motor drivers using IOFF during brown-out conditions. Use Value: Meets IEC 62304 Class C software safety requirements by guaranteeing deterministic latch state retention and preventing unintended actuator activation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal transparent latch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC373APWR | TI part with identical pinout and function but wider propagation delay range (2.5–6.5 ns at 3.3 V) and no IOFF specification. | Lacks guaranteed power-down isolation; unsuitable for hot-swap or multi-rail sequencing where backflow prevention is required. | Select only if IOFF is not needed and legacy TI supply chain preference exists. |
| 74LVC373PW,118 | Nexperia's standard-speed variant: same package and pinout, but rated only for -40 °C to +85 °C and lacks extended temperature qualification. | Not qualified for under-hood or industrial ambient extremes; lower thermal derating margin above 85 °C. | Choose for cost-sensitive commercial-grade applications where full -40 °C to +125 °C operation is unnecessary. |
Compared with SN74LVC373APWR and 74LVC373PW,118, the 74ALVC373PW,112 uniquely combines IOFF-enabled power-down safety, extended temperature operation, and tighter propagation delay consistency - making it the sole choice for automotive and industrial systems requiring guaranteed bus isolation during power transitions.
Availability
74ALVC373PW,112 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, test equipment digital pattern generation, and medical infusion pump controllers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74ALVC373PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74ALVC series targets advanced low-voltage digital interfacing, delivering enhanced speed-power trade-offs and robustness for mixed-signal systems operating across multiple supply rails.
FAQ
Does 74ALVC373PW,112 support hot-swap insertion?
Yes. Its IOFF circuitry actively disables outputs and blocks backflow current when VCC = 0 V, enabling safe insertion into live backplanes or powered subsystems. This feature complies with JEDEC JESD78 Class II.A latch-up immunity (>250 mA) and is validated for partial power-down operation per datasheet Section 1.
Can 74ALVC373PW,112 interface directly with 5 V TTL logic?
No. While inputs tolerate up to 3.6 V, the device operates only from 1.65 V to 3.6 V and cannot drive 5 V TTL-compatible logic levels. For 5 V interface, use a level translator such as the NTS0102 or a discrete resistor network with appropriate current limiting.
What is the minimum pulse width required on LE for reliable latching?
The minimum LE HIGH pulse width is 3.3 ns at VCC = 3.0–3.6 V (Table 7). This ensures sufficient time for internal metastability resolution and guarantees correct data capture from D inputs into latches without race conditions.
Is the TSSOP20 package RoHS-compliant and lead-free?
Yes. The SOT360-1 package used for 74ALVC373PW,112 is fully RoHS-compliant and lead-free, meeting EU Directive 2011/65/EU and Nexperia's environmental specifications per datasheet revision 4 (July 2023).
74ALVC373PW,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74ALVC
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 8:8
- Output Type:
- Tri-State
- Voltage - Supply:
- 1.65V ~ 3.6V
- Independent Circuits:
- 1
- Delay Time - Propagation:
- 2.2ns
- Current - Output High, Low:
- 24mA, 24mA
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP
74ALVC373PW,112 FAQ
1.How can I place an order for 74ALVC373PW,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74ALVC373PW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74ALVC373PW,112 reliable?
The price and inventory of 74ALVC373PW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74ALVC373PW,112 is usually 5 days.
3.What payment methods are accepted for 74ALVC373PW,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74ALVC373PW,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74ALVC373PW,112?
74ALVC373PW,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74ALVC373PW,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74ALVC373PW,112?
For technical support, including 74ALVC373PW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74ALVC373PW,112 requirements.
6.How does Aetrix verify that 74ALVC373PW,112 is sourced from the original manufacturer or authorized distributors?
All 74ALVC373PW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74ALVC373PW,112 meets industry standards.
7.What is the process for return or replacement of 74ALVC373PW,112?
All 74ALVC373PW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74ALVC373PW,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74ALVC373PW,112 part is unused and in its original packaging.
Return procedure for 74ALVC373PW,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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