Nexperia USA Inc. 74ALVT16373DGG,112

Overview

74ALVT16373DGG,112 from Nexperia is a 16-bit transparent D-type latch with 3-state outputs in TSSOP48 package, operating from 2.3 V to 3.6 V supply, featuring dual independent 8-bit latch enables (1LE/2LE) and output enables (1OE/2OE), bus-hold inputs eliminating external pull-ups, and ±64 mA/–32 mA output drive - used in high-speed bus interface and data buffering for industrial control backplanes.

For engineers reviewing the 74ALVT16373DGG,112 datasheet, 74ALVT16373DGG,112 pinout, 74ALVT16373DGG,112 application, or 74ALVT16373DGG,112 equivalent, this page delivers verified functional architecture, real-world timing behavior at 2.5 V and 3.3 V, latch transparency vs. storage mode behavior, bus-hold current specs, and precise 3-state propagation delays critical for synchronous bus arbitration and hot-swap I/O staging.

Technical Context

The device implements two independent 8-bit transparent latches sharing a common 48-pin TSSOP package, each controlled by dedicated active-HIGH latch enable (1LE/2LE) and active-LOW output enable (1OE/2OE). Latch transparency occurs when nLE = HIGH; data propagates with ≤2.9 ns tPHL (3.3 V), while storage is triggered on HIGH-to-LOW nLE transition with 0.2 ns minimum hold time for LOW-level inputs.

Bus-hold circuitry maintains stable logic states on unused data inputs without external resistors, drawing IBHL = 75–130 μA (LOW) and IBHH = –75 to –140 μA (HIGH) at 3.0 V. IOFF protection enables partial power-down operation, limiting leakage to ±100 μA when VCC = 0 V and VI/VO = 0–4.5 V.

Key Specifications

Pinout & Package

TSSOP48 package (SOT362-1), 48-pin plastic thin shrink small outline, 6.1 mm body width, 0.5 mm pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with SN74ALVTH16373ZRGR and 74LVT16373DGG,118, the 74ALVT16373DGG,112 uniquely combines 5 V input tolerance, integrated bus-hold, and industrial temperature range in a single TSSOP48 package - making it the only option requiring zero external components for robust hot-swap and mixed-voltage bus interfacing.

Availability

74ALVT16373DGG,112 is available at Aetrix Electronics and suitable for industrial backplane buffering, hot-swappable module interfaces, multi-processor shared memory, and high-speed test equipment data capture requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74ALVT16373DGG,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer applications.

The 74ALVT16373 belongs to Nexperia's Advanced Low-Voltage Technology (ALVT) logic family, engineered specifically for high-speed, low-power 2.5 V/3.3 V bus interface applications demanding robust noise immunity, live insertion capability, and seamless 5 V system interoperability.

FAQ

What is the maximum clock frequency supported by the 74ALVT16373DGG,112?

The device does not operate on a clock signal - it is a transparent latch controlled by level-sensitive enable inputs (1LE/2LE). Its usable data rate is determined by propagation delay (as low as 0.5 ns at 3.3 V) and setup/hold times (e.g., tsu(L) = 0.8 ns min at 3.3 V), enabling reliable operation in systems with bus cycles down to ~2 ns period, equivalent to 500 MHz effective throughput under ideal conditions.

Can the 74ALVT16373DGG,112 be used with a 5 V microcontroller?

Yes - its inputs tolerate up to 5.5 V regardless of VCC (2.3–3.6 V), and outputs drive 5 V TTL loads directly due to +64 mA/–32 mA drive strength and VOH ≥ 2.0 V at 3.0 V supply. No level shifters are required, though output voltage swing remains bounded by VCC, not 5 V.

How does bus-hold functionality eliminate external pull-up resistors?

Internal weak-feedback transistors actively maintain the last-valid logic state on each data input (1Dn/2Dn). At 3.0 V supply, IBHL = 75–130 μA (LOW) and IBHH = –75 to –140 μA (HIGH) provide sufficient current to overcome typical PCB leakage and noise, holding inputs stable without 10 kΩ external resistors - reducing BOM count and board space.

Is the 74ALVT16373DGG,112 suitable for hot-swap applications?

Yes - it supports live insertion/extraction via three key features: IOFF circuitry limits leakage to ±100 μA when VCC = 0 V, power-up 3-state keeps outputs high-Z until VCC exceeds 1.2 V, and bus-hold maintains defined logic states on floating inputs. These ensure no bus contention or latch corruption during hot-plug events in backplane systems.