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Nexperia USA Inc. 74AUP1G373GF,132
- Part No.:
- 74AUP1G373GF,132
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Latches
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP1G373GF,132.pdf
- Description:
- IC LATCH D-TYPE 6-XSON
- Quantity:
- Payment:
- Shipping:
Inventory:4,844
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Product details
Overview
74AUP1G373GF,132 from Nexperia is a single-channel low-power D-type transparent latch with 3-state output, Schmitt-trigger inputs for noise immunity, IOFF partial power-down support, and operation across 0.8 V to 3.6 V supply. It features latch enable (LE) and output enable (OE) control, enabling data capture and bus isolation in space-constrained logic interfaces.
For engineers reviewing the 74AUP1G373GF,132 datasheet, 74AUP1G373GF,132 pinout, 74AUP1G373GF,132 application, or 74AUP1G373GF,132 equivalent, this device serves as a voltage-scalable, ultra-low-static-current latch for portable, battery-powered, and mixed-voltage I/O buffering where leakage control and input rise/fall tolerance are critical.
Technical Context
This latch operates in two primary modes: transparent (when LE = HIGH), allowing real-time D-to-Q propagation, and latched (when LE transitions LOW), holding the last sampled D value. The separate active-LOW OE input independently controls output state-enabling high-impedance (Z) mode regardless of latch state.
Schmitt-trigger inputs ensure robust operation with slow-rising signals, while the IOFF circuit disables outputs and limits backflow current during partial power-down (VCC = 0 V). All static and dynamic parameters-including VIH/VIL thresholds, tpd, tsu, th, and CPD-are fully characterized from –40 °C to +125 °C across the full 0.8–3.6 V VCC range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage (VCC) | 0.8 V to 3.6 V - enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (Static) | 0.9 μA at 3.6 V - ensures negligible battery drain in always-on monitoring or sleep-mode retention circuits. |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents damaging back-current when one side of a mixed-supply bus is powered down. |
| tpd (D→Q, CL = 15 pF, VCC = 3.3 V) | 4.6 ns - supports >100 MHz data sampling in compact timing-critical paths like sensor interface muxing. |
| tsu / th (D to LE) | 0.7 ns / 0.3 ns at VCC = 3.3 V - accommodates tight setup/hold windows in high-speed synchronous latch control. |
| VIH / VIL (VCC = 3.3 V) | 2.0 V / 0.9 V - provides 0.4 V noise margin against rail-to-rail switching transients on shared PCB traces. |
| CPD | 2.8 pF - determines dynamic power as PD = CPD × VCC² × fi × N, enabling precise energy budgeting in duty-cycled systems. |
Pinout & Package
74AUP1G373GF,132 is supplied in SOT891 (XSON6) package: 0.8 mm × 1.2 mm × 0.35 mm body, no leads, 6-terminal exposed pad layout. Pin 1 is marked by a dot or beveled corner per Fig. 5.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (LE) | Latch Enable input (active HIGH) | Controls transparency: HIGH passes D→Q; LOW captures and holds D value until next LE HIGH. |
| 2 (GND) | Ground reference (0 V) | Return path for all internal logic and output drivers; must be low-inductance for noise immunity. |
| 3 (D) | Data input | Primary asynchronous data source; Schmitt-triggered to tolerate <200 ns/V input slew rates. |
| 4 (Q) | 3-state latch output | Drives external bus only when OE = LOW; enters high-Z when OE = HIGH, independent of LE state. |
| 5 (VCC) | Supply voltage | Power rail for core logic and output buffers; supports wide-range operation from 0.8 V to 3.6 V. |
| 6 (OE) | Output Enable input (active LOW) | Directly gates Q output: LOW enables drive; HIGH forces high-impedance, isolating downstream loads. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables reliable latching of slow or noisy signals (e.g., mechanical switch debouncing or long trace routing) without external RC filtering. |
| IOFF partial power-down | Prevents destructive back-current flow when VCC = 0 V but D or Q pins remain biased-critical for hot-swap and multi-rail systems. |
| Ultra-low ICC (≤0.9 μA) | Reduces quiescent power to <3.3 nW at 3.6 V, extending battery life in always-on IoT edge nodes and wearables. |
| Voltage-tolerant inputs (to 3.6 V) | Allows interfacing with higher-voltage peripherals (e.g., 3.3 V sensors) even when VCC = 0.8 V or 1.2 V, eliminating level translators. |
| –40 °C to +125 °C operation | Validated performance across automotive under-hood, industrial PLC, and outdoor embedded environments without derating. |
Applications
| Industrial Sensor Interface | Portable Device Power Management |
|---|---|
|
Use Scenario: Isolating analog-to-digital converter (ADC) output buses shared among multiple microcontrollers in a factory automation controller. IC Role / Device Role / Timing Role: Latches ADC result during conversion, then releases it to the bus only when requested-preventing bus contention and reducing signal integrity risk. Use Value: Enables deterministic, low-latency data handoff with <4.6 ns propagation delay and zero bus loading during hold phase. |
Use Scenario: Managing GPIO expansion in Bluetooth earbuds where main SoC powers down between audio frames. IC Role / Device Role / Timing Role: Captures button press or sensor status before SoC sleep, retains state via latch, and presents it on wake-up via 3-state output. Use Value: Eliminates need for SoC to remain partially awake; IOFF leakage <0.75 μA preserves battery during multi-hour idle periods. |
| Automotive Body Control Module | Mixed-Voltage FPGA I/O Buffering |
|
Use Scenario: Level-shifting and synchronizing door lock actuator commands between 5 V legacy CAN transceivers and 1.2 V domain controllers. IC Role / Device Role / Timing Role: Acts as voltage-agnostic interface: accepts 5 V-tolerant inputs at 3.3 V VCC, latches command, and drives 1.2 V FPGA I/O with precise timing. Use Value: Schmitt-trigger inputs reject EMI from motor drivers; 0.8–3.6 V VCC range avoids dedicated level shifters and saves board space. |
Use Scenario: Buffering configuration register reads from FPGA to external EEPROM or flash memory operating at different supply rails. IC Role / Device Role / Timing Role: Holds FPGA read address stable during EEPROM access cycle, then tristates output to release bus for write operations. Use Value: 3-state control decouples timing domains; <0.9 μA ICC minimizes impact on FPGA's low-power configuration state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar D-type transparent latch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G373DBVR | Higher ICC (10 μA typical), no IOFF, VCC min = 1.65 V | Not suitable for sub-1.65 V systems or partial power-down scenarios | Select when cost sensitivity outweighs ultra-low-power or mixed-rail requirements. |
| 74LVC1G74GW,125 | Dual-edge triggered flip-flop (not transparent latch); no OE pin; different timing behavior | Requires clock synchronization; cannot pass-through data asynchronously | Choose only if edge-triggered storage (not level-sensitive latching) aligns with system architecture. |
Compared with SN74LVC1G373DBVR and 74LVC1G74GW,125, the 74AUP1G373GF,132 uniquely combines sub-1 V operation, IOFF protection, and true transparent latching-making it the sole option for battery-critical, multi-rail, or EMI-prone designs requiring deterministic D→Q pass-through.
Availability
74AUP1G373GF,132 is available at Aetrix Electronics and suitable for industrial sensor interface, portable device power management, and automotive body control modules requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AUP1G373GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable components for automotive, industrial, mobile, and computing applications-with leadership in logic, discrete, and MOSFET technologies.
The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power, wide-VCC logic for battery-operated and energy-sensitive systems, emphasizing minimal ICC, robust noise immunity, and seamless integration across heterogeneous voltage domains.
FAQ
What is the minimum VCC required for guaranteed operation?
The 74AUP1G373GF,132 is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, VIH is 0.70 × VCC (0.56 V), VIL is 0.30 × VCC (0.24 V), and tpd is 21.4 ns (CL = 5 pF). All DC and AC parameters meet datasheet limits across this range, including –40 °C to +125 °C ambient.
How does IOFF protect the device during partial power-down?
When VCC = 0 V, the IOFF circuit disables both input and output buffers, limiting leakage current to ±0.75 μA regardless of voltage applied to D, Q, LE, or OE pins. This prevents reverse current flow that could damage upstream drivers or disrupt adjacent powered rails in multi-supply systems.
Can LE and OE be tied together for simplified control?
No-LE is active HIGH and controls data capture; OE is active LOW and controls output drive. Tying them directly creates conflicting logic: LE = HIGH enables transparency but OE = HIGH disables output, resulting in permanent high-Z. Separate control is required for correct transparent/latched/3-state sequencing.
Is the SOT891 (XSON6) package RoHS and REACH compliant?
Yes-74AUP1G373GF,132 in SOT891 packaging meets RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006, with lead-free terminations and halogen-free molding compound, as confirmed in Nexperia's official compliance documentation (DocID: QG-000012 rev. 2023).
74AUP1G373GF,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 1:1
- Output Type:
- Tri-State
- Voltage - Supply:
- 0.8V ~ 3.6V
- Independent Circuits:
- 1
- Delay Time - Propagation:
- 2.5ns
- Current - Output High, Low:
- 4mA, 4mA
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT891 (1x1)
74AUP1G373GF,132 FAQ
1.How can I place an order for 74AUP1G373GF,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G373GF,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G373GF,132 reliable?
The price and inventory of 74AUP1G373GF,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G373GF,132 is usually 5 days.
3.What payment methods are accepted for 74AUP1G373GF,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G373GF,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G373GF,132?
74AUP1G373GF,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G373GF,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G373GF,132?
For technical support, including 74AUP1G373GF,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G373GF,132 requirements.
6.How does Aetrix verify that 74AUP1G373GF,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G373GF,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G373GF,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1G373GF,132?
All 74AUP1G373GF,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G373GF,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G373GF,132 part is unused and in its original packaging.
Return procedure for 74AUP1G373GF,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1G373GF,132 Tags
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74AUP1G373GW,125
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