Nexperia USA Inc. 74AUP1G373GN,132

Overview

74AUP1G373GN,132 from Nexperia is a single-channel low-power D-type transparent latch with 3-state output and Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply. It features latch enable (LE) and output enable (OE) control, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C in the ultra-compact XSON6 (SOT1115) package (0.9 × 1.0 × 0.35 mm). Used for data latching and bus isolation in portable sensor interfaces and low-voltage microcontroller I/O expansion.

For engineers reviewing the 74AUP1G373GN,132 datasheet, 74AUP1G373GN,132 pinout, 74AUP1G373GN,132 application, or 74AUP1G373GN,132 equivalent, key selection criteria include its sub-1 μA static ICC, IOFF-enabled hot-swap capability, Schmitt-trigger noise immunity, and compatibility with 1.2 V, 1.8 V, and 3.3 V logic domains in space-constrained designs.

Technical Context

This device implements a transparent latch architecture where Q follows D when LE is HIGH, and holds the last value when LE transitions LOW. The separate active-LOW OE input controls output tri-state behavior independently of latching, enabling shared-bus applications without data contention.

Its Schmitt-trigger inputs tolerate slow-rising signals and reject noise up to ±100 mV hysteresis, while the IOFF circuit disables outputs and blocks backflow current when VCC = 0 V - critical for partial power-down sequencing in multi-rail systems.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount with 0.9 mm × 1.0 mm body and 0.35 mm height. Pin 1 indicator located on lower-left corner below marking code "aW".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type transparent latch applications.

Compared with SN74LVC1G373DBVR and 74LVC1G74GW,125, the 74AUP1G373GN,132 uniquely combines ultra-low ICC, IOFF protection, and transparent latching in the smallest XSON6 variant - making it optimal for space- and power-constrained always-on sensing nodes.

Availability

74AUP1G373GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and IoT edge node data aggregation requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G373GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable components for automotive, industrial, and consumer applications, with leadership in logic, MOSFETs, and ESD protection.

The 74AUP1G373GN,132 belongs to the AUP (Advanced Ultra-low Power) logic family, engineered specifically for battery-operated and thermally constrained systems demanding sub-microwatt static power and robust multi-voltage interoperability.

FAQ

What is the minimum VCC required for guaranteed operation?

The 74AUP1G373GN,132 is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, VIH is 0.70 × VCC (≥0.56 V), VIL is 0.30 × VCC (≤0.24 V), and propagation delay remains within 21.4 ns (CL = 5 pF). This enables direct integration with 0.8 V-core processors and energy-harvesting PMICs.

How does IOFF protect the device during partial power-down?

When VCC = 0 V, the IOFF circuitry disables both input and output buffers, limiting leakage to ±0.75 μA regardless of signal levels on D, LE, OE, or Q. This prevents reverse current flow through the device - a critical safeguard during hot-swap, rail sequencing, or brown-out conditions in multi-supply systems.

Can the 74AUP1G373GN,132 drive a 50 pF load?

No - the datasheet specifies timing and drive performance only up to CL = 30 pF. At CL = 50 pF, propagation delay increases beyond guaranteed limits (e.g., D→Q exceeds 7.9 ns at VCC = 3.3 V), and output rise/fall times degrade. For >30 pF loads, add series termination or use a buffer stage.

Is the Schmitt-trigger hysteresis value specified in the datasheet?

The datasheet does not publish absolute hysteresis voltage (ΔV) but confirms Schmitt-trigger action with typical input hysteresis ≥100 mV across VCC = 0.8–3.6 V, based on VIH/VIL separation (e.g., at VCC = 3.3 V: VIH ≥ 2.0 V, VIL ≤ 0.9 V → ΔV ≥ 1.1 V). Measured hysteresis meets JEDEC JESD8-12/8-11 requirements.