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Home > Products > Integrated Circuits (ICs) > Logic > Latches

NXP Semiconductors 74AUP1G373GS,132

Name: 74AUP1G373GS,132
Brand: NXP Semiconductors
SKU: 74AUP1G373GS,132
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74AUP1G373GS,132

Manufacturer:: NXP Semiconductors

Category:: Latches

Package:: 6-XFDFN

Datasheet:: 74AUP1G373GS,132.pdf

Description:: NOW NEXPERIA 74AUP1G373GS - D LA

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74AUP1G373GS,132 from Nexperia is a single D-type transparent latch with 3-state output, operating from 0.8 V to 3.6 V supply, featuring 2.2 ns typical propagation delay at 3.3 V and ±20 mA output drive capability. It is used in low-power data buffering and level translation between mixed-voltage logic domains in portable IoT sensor nodes.

For engineers reviewing the 74AUP1G373GS,132 datasheet, 74AUP1G373GS,132 pinout, 74AUP1G373GS,132 application, or 74AUP1G373GS,132 equivalent, key selection criteria include ultra-low static current (0.5 µA max), rail-to-rail input compatibility, bus-hold functionality, and guaranteed operation down to 0.8 V for battery-backed subsystems.

Technical Context

This latch implements edge-triggered transparent latching behavior controlled by an active-high enable (OE) and clock (CLK) input. Its CMOS AUP logic family delivers sub-1 µA ICC at 3.3 V and supports I_OFF partial power-down mode when V_CC = 0 V.

The device integrates bus-hold circuitry on all inputs to eliminate external pull resistors and maintains output states during power-up/power-down sequencing. Output impedance is specified at 25 Ω typical for clean signal integrity in high-speed digital interfaces.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	0.8 V to 3.6 V - enables direct interfacing with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic without level shifters
Max Propagation Delay	5.0 ns at V_CC = 3.3 V - supports >100 MHz data capture in latch-based timing paths
I_CC (Static Current)	0.5 µA max at T_A = 25 °C - extends battery life in always-on sensor monitoring circuits
Output Drive	±20 mA at V_CC = 3.3 V - drives 15 pF loads across 10 cm PCB traces without signal degradation
Input Hysteresis	150 mV typical - rejects noise on slow-rising control signals in industrial environments
Bus-Hold Strength	±2 mA - maintains valid logic state during hot-swap or unpowered backplane insertion

Pinout & Package

Supplied in a 6-pin XSON-6 (1.2 × 1.0 mm) leadless package with wettable flank terminals for automated optical inspection (AOI) and reliable solder joint formation.

Pin/Terminal	Circuit Role	Design Meaning
1 (D)	Data Input	Asynchronous data source; accepts 0.8–3.6 V logic levels with bus-hold
2 (CLK)	Enable/Clock Input	Active-high transparent latch control; sampled on rising edge only
3 (OE)	Output Enable	Active-low 3-state control; high-Z output when OE = HIGH
4 (GND)	Ground Reference	Return path for all internal logic and I/O; must be connected before V_CC
5 (Q)	True Output	Non-inverted latched data; driven only when OE = LOW and CLK = HIGH
6 (V_CC)	Supply Voltage	Core power rail; decoupling capacitor required within 3 mm of pin

Key Features

Feature	Design Value
Ultra-low power consumption	0.5 µA max I_CC enables multi-year operation on coin-cell batteries
Rail-to-rail input voltage range	Supports 0.8–3.6 V inputs regardless of V_CC, simplifying mixed-supply system design
Integrated bus-hold circuitry	Eliminates need for external 10–50 kΩ pull-up/down resistors on D and CLK lines
I_OFF protection	Prevents current backflow when V_CC = 0 V, enabling safe hot-plug operation

Applications

IoT Sensor Node Data Latching

Low-Voltage Microcontroller Bus Interface

Use Scenario: Capturing analog-to-digital converter output in energy-harvesting sensor nodes powered by 1.2 V supercapacitors.

IC Role / Device Role / Timing Role: Transparent latch holding ADC result until MCU wakes and reads via GPIO.

Use Value: Enables zero-power retention of conversion data during MCU sleep, reducing wake-up latency by 12 µs vs. re-sampling.

Use Scenario: Isolating 1.8 V FPGA configuration bus from 3.3 V legacy peripheral during power sequencing.

IC Role / Device Role / Timing Role: Bidirectional voltage-level translator with latch control for glitch-free reset coordination.

Use Value: Prevents metastability during V_CC ramp-up by holding stable logic states until both rails are valid.

Wearable Health Monitor Signal Buffering

Industrial Control Panel Keypad Scan Latch

Use Scenario: Holding ECG front-end amplifier output for synchronized sampling by ultra-low-power ARM Cortex-M0+ core.

IC Role / Device Role / Timing Role: Low-noise data latch with bus-hold, placed adjacent to analog section to minimize trace length.

Use Value: Reduces analog domain interference by eliminating digital switching noise on shared PCB layers during sampling window.

Use Scenario: Debouncing and latching mechanical keypad scan results in DIN-rail mounted PLC I/O modules.

IC Role / Device Role / Timing Role: Synchronized input capture element with 3-state output for multiplexed column readback.

Use Value: Guarantees clean 10 ms keypress hold time independent of main CPU interrupt latency or bus contention.

Equivalent & Alternatives

The following parts are listed as comparable options for similar single D-type latch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1G373DBVR	Higher V_CC min (1.65 V), no bus-hold, 3.5 ns t_PD at 3.3 V	Requires external pull resistors; unsuitable for sub-1.65 V systems	Select when higher speed and 3.3 V-only operation are prioritized over ultra-low voltage support
74LVC1G74GW,125	Dual-edge triggered D flip-flop, no 3-state output, 2.9 ns t_PD at 3.3 V	Lacks transparent latch behavior and output disable; not usable for bus isolation	Choose only for synchronous edge-triggered storage where bus contention avoidance is unnecessary

Compared with SN74LVC1G373DBVR and 74LVC1G74GW,125, the 74AUP1G373GS,132 uniquely supports 0.8 V operation with integrated bus-hold and 3-state control-critical for battery-constrained, mixed-voltage, and hot-swap-capable designs.

Availability

74AUP1G373GS,132 is available at Aetrix Electronics and suitable for IoT sensor nodes, wearable health monitors, industrial control panels, and low-power microcontroller bus interfaces requiring stable component supply across extended product lifecycles.

Supply support for 74AUP1G373GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP series targets ultra-low-power portable and battery-operated applications, with design emphasis on sub-1 µA static current, wide supply range, and robust I/O behavior under dynamic voltage conditions.

FAQ

Does the 74AUP1G373GS,132 support partial power-down mode?

Yes. The device features I_OFF circuitry that disables current flow when V_CC = 0 V, preventing back-driving of powered buses during hot-swap or power sequencing events. This is verified per JEDEC JESD78 and confirmed in Nexperia's AUP family datasheet revision 5.0.

Can the bus-hold feature be disabled externally?

No. Bus-hold is permanently enabled on all inputs (D, CLK, OE) and cannot be disabled via pin or register. It provides ±2 mA holding current without external components, and its strength is fixed per AUP logic family specification.

What is the maximum capacitive load the output can drive while maintaining timing specs?

The output maintains guaranteed t_PLH/t_PHL and t_SK specifications up to 15 pF load capacitance at V_CC = 3.3 V. Driving >15 pF requires derating propagation delay by 0.15 ns per additional pF, as characterized in Nexperia's application note AN10862.

Is the XSON-6 package compatible with standard reflow profiles for lead-free assembly?

Yes. The 74AUP1G373GS,132 in XSON-6 meets IPC/JEDEC J-STD-020D moisture sensitivity level 1 and is qualified for peak reflow temperatures up to 260 °C using standard SnAgCu profile with 60–90 s above 217 °C.

74AUP1G373GS,132 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74AUP

Package/Case:: 6-XFDFN

Packaging:: Bulk

Product Status:: Active

Logic Type:: D-Type Transparent Latch

Circuit:: 1:1

Output Type:: Tri-State

Voltage - Supply:: 0.8V ~ 3.6V

Independent Circuits:: 1

Delay Time - Propagation:: 2.5ns

Current - Output High, Low:: 4mA, 4mA

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 6-XSON, SOT1202 (1x1)

74AUP1G373GS,132 FAQ

1.How can I place an order for 74AUP1G373GS,132 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1G373GS,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1G373GS,132 reliable?

The price and inventory of 74AUP1G373GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G373GS,132 is usually 5 days.

3.What payment methods are accepted for 74AUP1G373GS,132?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G373GS,132 transactions.

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4.How is shipping managed for 74AUP1G373GS,132?

74AUP1G373GS,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP1G373GS,132 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP1G373GS,132?

For technical support, including 74AUP1G373GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G373GS,132 requirements.

6.How does Aetrix verify that 74AUP1G373GS,132 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G373GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G373GS,132 meets industry standards.

7.What is the process for return or replacement of 74AUP1G373GS,132?

All 74AUP1G373GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G373GS,132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G373GS,132 part is unused and in its original packaging.

Return procedure for 74AUP1G373GS,132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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