Nexperia USA Inc. 74AUP1G373GW-Q100H

Overview

74AUP1G373GW-Q100 from Nexperia is a single-channel automotive-grade D-type transparent latch with 3-state output, Schmitt-trigger inputs, IOFF partial power-down support, and operation across 0.8 V to 3.6 V supply. It provides latch enable (LE), output enable (OE), and data retention in automotive body control modules, infotainment I/O expansion, and ADAS sensor interface buffering.

For engineers reviewing the 74AUP1G373GW-Q100 datasheet, 74AUP1G373GW-Q100 pinout, 74AUP1G373GW-Q100 application, or 74AUP1G373GW-Q100 equivalent, this page delivers verified functional behavior, AEC-Q100 Grade 1 qualification details, low-voltage timing specs, IOFF leakage limits, and TSSOP6 package implementation guidance.

Technical Context

This device implements a transparent latch architecture where Q follows D when LE is HIGH, latches D on LE HIGH-to-LOW transition, and places Q in high-impedance state when OE is HIGH. The dual-control logic (LE for data capture, OE for output gating) enables precise bus isolation and signal staging in mixed-voltage automotive subsystems.

Schmitt-trigger inputs tolerate slow-rising signals up to 200 ns/V, while IOFF circuitry ensures sub-0.75 μA backflow current when VCC = 0 V - critical for hot-swap and power sequencing in 12 V/48 V vehicle architectures. All static and dynamic parameters are fully characterized from −40 °C to +125 °C.

Key Specifications

Pinout & Package

TSSOP6 plastic thin shrink small outline package (SOT363-2), 1.25 mm body width, 0.65 mm lead pitch, 6-pin surface-mount configuration with pin 1 indicator below marking code 'aW'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type transparent latch applications.

Compared with SN74LVC1G373DBVR and 74LVC1G74GW-Q100, the 74AUP1G373GW-Q100 uniquely combines AEC-Q100 Grade 1 qualification, IOFF-enabled partial power-down, Schmitt-trigger inputs, and true transparent latch + 3-state output functionality - making it the sole fit for automotive bus isolation and power-gated sensor interfaces.

Availability

74AUP1G373GW-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, ADAS sensor interfaces, infotainment I/O expansion, and radar diagnostic logging requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G373GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for automotive, industrial, and mobile applications with emphasis on reliability and energy efficiency.

This device belongs to the 74AUP ultra-low-power logic family, engineered specifically for automotive subsystems demanding wide VCC range, AEC-Q100 compliance, and robust power sequencing behavior.

FAQ

What is the maximum operating frequency supported by the 74AUP1G373GW-Q100?

The device does not specify a maximum clock frequency because it is a transparent latch, not a clocked flip-flop. Its usable speed is defined by propagation delay: tpd(D→Q) is 1.2 ns min to 4.0 ns max at VCC = 3.3 V and CL = 5–30 pF. System-level timing depends on LE pulse width (≥0.8 ns min at 3.3 V) and data setup/hold windows.

Can the 74AUP1G373GW-Q100 interface directly with 5 V logic?

No. Absolute maximum input voltage is +4.6 V, but overvoltage tolerance applies only when VCC ≤ 3.6 V - inputs must not exceed VCC + 0.3 V per JEDEC JESD8C. For 5 V systems, a level translator or resistor-divider network is required; direct connection risks damage or undefined logic states.

How does the IOFF feature behave during power sequencing?

When VCC drops to 0 V, the IOFF circuit disables output drivers and limits reverse current to ±0.75 μA maximum, preventing backfeed from powered buses into unpowered sections. This enables safe hot-swap of ECUs and independent power domain shutdown without latch-up risk or signal corruption.

Is the Schmitt-trigger input threshold fixed or VCC-dependent?

Schmitt-trigger thresholds scale with VCC: VIH(min) = 0.70 × VCC at 0.8 V, 0.65 × VCC at 0.9–1.95 V, and fixed 1.6 V/2.0 V at higher rails; VIL(max) = 0.25–0.35 × VCC depending on VCC range. Hysteresis is typically 0.3 × VCC, ensuring noise margins >300 mV across full supply range.