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Nexperia USA Inc. 74HC373D,653

Part No.:
74HC373D,653
Manufacturer:
Nexperia USA Inc.
Category:
Latches
Package:
20-SOIC (0.295", 7.50mm Width)
Datasheet:
Aetrix74HC373D,653.pdf
Description:
IC D-TYPE TRANSP SGL 8:8 20SO
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:4,624

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Product details

Overview

74HC373D,653 from Nexperia is an octal D-type transparent latch with 3-state outputs, used for bus interface and data hold in microcontroller peripheral expansion, memory address latching, and I/O port buffering. It operates from 2.0 V to 6.0 V, features active-HIGH latch enable (LE) and active-LOW output enable (OE), and is rated for -40 °C to +125 °C.

For engineers reviewing the 74HC373D,653 datasheet, 74HC373D,653 pinout, 74HC373D,653 application, or 74HC373D,653 equivalent, key selection criteria include propagation delay (15 ns typ @ 4.5 V), 3-state output drive capability (±7.8 mA), input voltage compatibility (CMOS-level), thermal rating (125 °C), and SO20 package mechanical fit.

Technical Context

The 74HC373D,653 implements eight independent D-latch cells with shared LE and OE controls. Its transparent mode allows real-time input-to-output tracking while LE is HIGH; a HIGH-to-LOW LE transition captures and holds data at the setup time prior to the edge. OE independently places all eight outputs in high-impedance state without affecting internal latch states.

Input clamp diodes enable safe interfacing to voltages exceeding VCC when current-limiting resistors are used. The device complies with JEDEC JESD7A (2.0–6.0 V) and JESD8C (2.7–3.6 V), supports 50 pF load capacitance, and exhibits CMOS-level input thresholds (VIH = 3.15 V min @ VCC = 4.5 V).

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage Range2.0 V to 6.0 V - Supports mixed-voltage system interfacing and battery-powered operation down to 2 V.
Propagation Delay (D→Q)15 ns typical @ VCC = 4.5 V, CL = 50 pF - Enables reliable timing in 33 MHz bus cycles with margin.
Output Drive Strength±7.8 mA @ VCC = 4.5 V - Sufficient to drive standard TTL loads and multiple CMOS inputs on shared buses.
Input ThresholdsVIH = 3.15 V min, VIL = 1.35 V max @ VCC = 4.5 V - Ensures robust noise immunity (>1.3 V DC noise margin).
Operating Temperature-40 °C to +125 °C - Qualified for industrial and under-hood automotive auxiliary applications.
Power Dissipation500 mW max (SO20) - Allows full-load operation at elevated ambient with appropriate PCB copper area.
ESD ProtectionHBM >2000 V, CDM >1000 V - Reduces need for external protection in board-level ESD zones.

Pinout & Package

74HC373D,653 is housed in a plastic small outline package (SO20, SOT163-1) with 20 leads, 7.5 mm body width, and gull-wing leads. Pin 1 is marked by a bevelled corner or index notch.

Pin/Terminal Circuit Role Design Meaning
1 (OE)3-state output enableActive-LOW control: drives all Q0–Q7 into high-Z when HIGH; no effect on latch state.
2–9, 12–15, 17–19 (Q0–Q7, D0–D7)latch outputs / data inputsQn and Dn pins are paired per bit; Dn feeds Qn only during LE HIGH (transparent mode).
10 (GND)ground referencePrimary return path for all internal logic and output currents; must be low-impedance.
11 (LE)latch enableActive-HIGH: enables transparency; HIGH-to-LOW edge captures Dn values with 10 ns setup/hold window @ 4.5 V.
20 (VCC)supply voltagePower rail for all logic and output stages; requires local 100 nF decoupling near pin 20.

Key Features

Feature Design Value
Wide supply range2.0–6.0 V operation enables direct use with 3.3 V microcontrollers and legacy 5 V systems without level shifters.
Clamp diode inputsIntegrated input diodes allow safe connection to signals up to VCC + 0.5 V using series resistors - simplifies mixed-supply interfacing.
Latch-up immunityExceeds 100 mA per JESD78 Class II Level B - ensures robustness against transient ground bounce or supply glitches.
3-state bus compatibilityCommon OE pin enables clean bus sharing across multiple devices; outputs float to high-Z without leakage or contention.
Industrial temperature gradeSpecified from -40 °C to +125 °C - validated for continuous operation in motor control enclosures and power supply modules.

Applications

Microcontroller Bus Expansion Memory Address Latching

Use Scenario: Expanding GPIO count of an ARM Cortex-M0+ MCU by adding parallel peripherals via 8-bit data bus.

IC Role / Device Role / Timing Role: Acts as bidirectional data latch between MCU data bus and peripheral registers, synchronized to WR strobe via LE.

Use Value: Eliminates need for dedicated bus transceivers; enables simultaneous read/write handshaking with 15 ns timing margin at 33 MHz.

Use Scenario: Holding upper address bits during multiplexed address/data bus cycles in 8051-based embedded systems.

IC Role / Device Role / Timing Role: Captures A8–A15 during AD0–AD7 address phase, then presents stable address to SRAM/Flash during data phase.

Use Value: Reduces external logic count; meets 20 ns address hold requirement with 10 ns setup/hold margin at 12 MHz system clock.

Industrial I/O Port Buffering Legacy System Interface Adapter

Use Scenario: Isolating PLC digital input module from noisy 24 V field wiring using optocoupler arrays.

IC Role / Device Role / Timing Role: Buffers conditioned 3.3 V logic levels from opto outputs into a common backplane bus, controlled by central FPGA.

Use Value: Provides 8-channel fan-out with ±7.8 mA drive and 125 °C rating - sustains reliability in uncooled control cabinets.

Use Scenario: Interfacing modern 3.3 V SoC to legacy ISA-bus peripherals requiring 5 V TTL-compatible latching.

IC Role / Device Role / Timing Role: Translates and latches ISA address/data signals using 5 V supply, with OE tied to ISA IOR/IOW.

Use Value: Maintains full 5 V noise margin (VIH = 2.0 V min for TTL) while consuming <100 μA static current - extends adapter board lifetime.

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Alternative Part Technical Difference Application Difference Selection Advice
74HCT373D,653TTL-compatible inputs (VIH = 2.0 V min); identical SO20 package and pinout.Better interoperability with 5 V TTL logic families; slightly higher ICC (80 μA vs 8 μA @ 25 °C).Select when interfacing legacy 5 V logic without level shifters.
SN74HC373PWRTexas Instruments TSSOP-20 package (SOT360-1); same electrical specs but 4.4 mm body width.Enables higher PCB density; requires rework of footprint and stencil; thermal resistance 100 K/W vs 120 K/W for SO20.Select for space-constrained designs where thermal derating is acceptable.

Compared with 74HCT373D,653, the 74HC373D,653 offers lower static power and CMOS input thresholds ideal for 3.3 V-native systems, while SN74HC373PWR trades package size for layout flexibility - neither is pin-compatible without footprint revision.

Availability

74HC373D,653 is available at Aetrix Electronics and suitable for microcontroller bus expansion, memory address latching, and industrial I/O port buffering requiring stable component supply across extended temperature ranges.

Supply support for 74HC373D,653 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for industrial, automotive, and computing markets.

The 74HC373 belongs to Nexperia's HC logic family, designed for low-power, wide-supply-voltage bus interface and data capture in resource-constrained embedded systems.

FAQ

Can 74HC373D,653 operate reliably at 2.0 V supply?

Yes. The device is fully specified from 2.0 V to 6.0 V, with guaranteed propagation delay ≤150 ns and output drive ≥±4 mA at 2.0 V. Input thresholds scale with VCC (VIH = 1.5 V min), ensuring correct logic interpretation across the full range.

What is the maximum capacitive load the outputs can drive?

The outputs are characterized up to 50 pF load capacitance per pin, with propagation delay and transition time data provided for that condition. Driving >50 pF increases tpd and tt linearly; for 100 pF, expect ~2× delay increase based on CL-dependent CPD (45 pF/latch).

Is there a risk of bus contention when OE is toggled during LE HIGH?

No. OE controls only output drivers; it has no effect on internal latch states or input buffers. Outputs transition cleanly between active and high-Z regardless of LE state, eliminating contention during dynamic bus arbitration.

How does the 74HC373D,653 handle input voltages above VCC?

Input clamp diodes allow safe operation with VI up to VCC + 0.5 V when series current-limiting resistors are used. For example, with 1 kΩ resistor and 7 V input at VCC = 5 V, clamping current remains below 20 mA absolute maximum rating.

74HC373D,653 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74HC
Package/Case:
20-SOIC (0.295", 7.50mm Width)
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
D-Type Transparent Latch
Circuit:
8:8
Output Type:
Tri-State
Voltage - Supply:
2V ~ 6V
Independent Circuits:
1
Delay Time - Propagation:
12ns
Current - Output High, Low:
7.8mA, 7.8mA
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
20-SO

74HC373D,653 FAQ

1.How can I place an order for 74HC373D,653 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HC373D,653 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HC373D,653 reliable?

The price and inventory of 74HC373D,653 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC373D,653 is usually 5 days.

3.What payment methods are accepted for 74HC373D,653?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC373D,653 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74HC373D,653?

74HC373D,653 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HC373D,653 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HC373D,653?

For technical support, including 74HC373D,653 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC373D,653 requirements.

6.How does Aetrix verify that 74HC373D,653 is sourced from the original manufacturer or authorized distributors?

All 74HC373D,653 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC373D,653 meets industry standards.

7.What is the process for return or replacement of 74HC373D,653?

All 74HC373D,653 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC373D,653, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HC373D,653 part is unused and in its original packaging.

Return procedure for 74HC373D,653:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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