Nexperia USA Inc. 74HC373DB,112

Overview

74HC373DB,112 from Nexperia is an octal D-type transparent latch with 3-state outputs, designed for bus-oriented data latching in digital systems. It features independent latch enable (LE, active HIGH) and output enable (OE, active LOW), operates from 2.0 V to 6.0 V, supports -40 °C to +125 °C, and delivers propagation delay as low as 12 ns at VCC = 6.0 V. It is used in microcontroller address/data bus isolation and memory interface buffering.

For engineers reviewing the 74HC373DB,112 datasheet, 74HC373DB,112 pinout, 74HC373DB,112 application, or 74HC373DB,112 equivalent, this device serves as a CMOS-level-compatible octal latch for bidirectional bus control, requiring precise timing validation for LE/OE setup/hold and output enable/disable transitions in high-density PCB layouts.

Technical Context

The 74HC373DB,112 implements eight independent D-type latches with transparent mode when LE is HIGH and storage mode on HIGH-to-LOW LE transition. Each latch has non-inverting 3-state output controlled solely by OE, with no effect on internal state during output disable.

Input clamping diodes allow safe interfacing to voltages exceeding VCC using current-limiting resistors. The device complies with JEDEC JESD7A (2.0–6.0 V) and JESD8C (2.7–3.6 V), and meets HBM ESD >2000 V and CDM >1000 V per JS-001/JS-002.

Key Specifications

Pinout & Package

74HC373DB,112 is packaged in SOT339-1 (SSOP20): plastic shrink small outline package, 20 leads, body width 5.3 mm, 0.65 mm pitch. Pin 1 index located at top-left corner with beveled edge marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with 74HC373DB,112, the SO20 variant offers easier hand-soldering but sacrifices board density and thermal efficiency, while the TSSOP20 improves miniaturization and cooling at the cost of rework difficulty - selection depends on assembly method and thermal envelope constraints.

Availability

74HC373DB,112 is available at Aetrix Electronics and suitable for microcontroller bus interfaces, memory address latching, and industrial I/O expansion requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74HC373DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on reliability, efficiency, and scalability for industrial and automotive markets.

The 74HC373DB,112 belongs to Nexperia's HC-series logic family, engineered for low-power, high-noise-immunity digital interfacing in harsh environments - targeting applications where signal integrity and long-term supply stability are critical.

FAQ

What is the maximum clock frequency supported by the 74HC373DB,112?

The 74HC373DB,112 does not operate on a clock signal; it is a transparent latch controlled by level-sensitive LE and OE inputs. Its usable data rate is determined by propagation delay (12 ns typ. at 6 V) and setup/hold times (9 ns su / 5 ns h at 6 V), enabling reliable operation in systems with bus cycles down to ~30 ns minimum period.

Can the 74HC373DB,112 interface directly with 3.3 V microcontrollers?

Yes - the 74HC373DB,112 supports VCC as low as 2.0 V and has CMOS-compatible input thresholds that scale with supply voltage. At VCC = 3.3 V, VIH ≈ 2.3 V and VIL ≈ 1.0 V, ensuring full compatibility with standard 3.3 V logic outputs without level translation.

Is there a pin-compatible TTL version of this device?

Yes - the 74HCT373DB,112 is functionally identical and pin-compatible, but uses TTL-compatible input thresholds (VIH = 2.0 V min, VIL = 0.8 V max at VCC = 4.5–5.5 V), making it suitable for interfacing with legacy 5 V TTL outputs while maintaining CMOS output drive characteristics.

How does the 3-state output behavior interact with latch state during OE assertion?

Asserting OE (driving it LOW) places Q0–Q7 outputs in high-impedance mode without altering the internal latch state. The stored data remains intact and immediately appears on outputs when OE is deasserted (HIGH), preserving data integrity across bus arbitration cycles.