Nexperia USA Inc. 74HC373DB,118
- Part No.:
- 74HC373DB,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Latches
- Package:
- 20-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74HC373DB,118.pdf
- Description:
- IC D-TYPE TRANSP SGL 8:8 20SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,481
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Product details
Overview
74HC373DB,118 from Nexperia is an octal D-type transparent latch with 3-state outputs, designed for bus-oriented digital systems requiring data latching and controlled output isolation. It operates across 2.0 V to 6.0 V supply, features independent latch enable (LE) and output enable (OE) inputs, and supports -40 °C to +125 °C operation in SO20 package. Used in microcontroller address/data bus buffering and memory interface circuits.
For engineers reviewing the 74HC373DB,118 datasheet, 74HC373DB,118 pinout, 74HC373DB,118 application, or 74HC373DB,118 equivalent, this page delivers verified functional behavior, SO20 pin mapping, propagation delay (15 ns typ @ 4.5 V), 3-state timing specs, and direct alternatives for bus latch replacement in industrial control and embedded I/O expansion designs.
Technical Context
The device implements eight independent D-type latches with transparent mode when LE is HIGH and edge-triggered capture on LE HIGH-to-LOW transition. Each latch output connects to a common 3-state buffer controlled solely by OE - enabling full bus sharing without affecting stored data.
Input clamping diodes allow safe interfacing to voltages exceeding VCC when used with current-limiting resistors. CMOS-level inputs (74HC variant) ensure compatibility with 3.3 V and 5 V logic families while maintaining low static current (≤8 μA typ at 25 °C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - Supports mixed-voltage system integration including 3.3 V and 5 V domains. |
| Propagation Delay (D→Q) | 15 ns typical at VCC = 4.5 V, CL = 50 pF - Enables reliable 33 MHz bus operation with margin. |
| 3-State Enable/Disable Time | 16 ns / 17 ns typical at VCC = 4.5 V - Ensures clean bus turnaround without contention during output transitions. |
| Output Drive Strength | ±7.8 mA at VCC = 4.5 V - Sufficient to drive 10 LSTTL loads or 50 pF trace capacitance. |
| Operating Temperature | -40 °C to +125 °C - Qualified for extended industrial and automotive under-hood applications. |
| Input Logic Level | CMOS-compatible - VIH = 3.15 V min, VIL = 1.35 V max at VCC = 4.5 V; eliminates need for level shifters. |
| Power Dissipation | 8 μA ICC typical at 25 °C - Enables low-quiescent-power hold states in battery-backed systems. |
Pinout & Package
74HC373DB,118 is supplied in SO20 (SOT163-1) plastic small outline package: 20-pin, 7.5 mm body width, 1.27 mm pitch, gull-wing leads. Pin 1 index located at top-left corner with notch marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | 3-State Output Enable | Active LOW control; asserts high-impedance state on all Q0–Q7 outputs regardless of latch content. |
| 2–9, 12–15, 16, 19 (Q0–Q7) | Latched Data Outputs | Non-inverting 3-state outputs; reflect stored D-input values when OE = LOW and LE has captured data. |
| 3–4, 7–8, 13–14, 17–18 (D0–D7) | Data Inputs | Asynchronous inputs passed directly to outputs during LE = HIGH (transparent mode); sampled on LE ↓ edge. |
| 10 (GND) | Ground Reference | Primary 0 V return path for logic and power; must be low-inductance connection for noise immunity. |
| 11 (LE) | Latch Enable | Active HIGH input; enables transparency when HIGH, captures Dn values on HIGH-to-LOW transition. |
| 20 (VCC) | Supply Voltage | Positive rail for internal logic and output drivers; decoupling capacitor required within 10 mm of pin. |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Range | 2.0 V to 6.0 V operation allows direct use in 3.3 V FPGA I/O banks and legacy 5 V microcontroller buses. |
| Independent Control Logic | Separate LE and OE inputs permit simultaneous latching and bus release - critical for pipelined memory access. |
| Clamped Inputs | Integrated input clamp diodes enable safe overvoltage tolerance up to ±20 mA, simplifying interface to higher-voltage sensors. |
| High Noise Immunity | Typical noise margin >1.3 V at VCC = 4.5 V ensures robust operation in electrically noisy PLC backplanes. |
| ESD Protection | HBM >2000 V and CDM >1000 V meet IEC 61000-4-2 Level 3 requirements for production handling. |
Applications
| Industrial PLC I/O Expansion | Microcontroller Address Latching |
|---|---|
Use Scenario: Isolating and latching parallel I/O signals between a main controller and modular field I/O cards in harsh factory environments. IC Role / Device Role / Timing Role: Acts as bidirectional data latch and bus isolator, synchronizing asynchronous sensor/actuator data to the controller's clock domain via LE timing. Use Value: Prevents bus contention during hot-swap of I/O modules and enables deterministic read/write cycles with <15 ns propagation delay. |
Use Scenario: Capturing lower-address bits during multiplexed AD bus operation in 8051 or AVR-based systems. IC Role / Device Role / Timing Role: Transparently passes address lines while LE is HIGH, then holds stable address during data phase when LE goes LOW. Use Value: Eliminates external glue logic for address demultiplexing, reducing BOM count and PCB area in space-constrained designs. |
| Memory Interface Buffering | Digital Test Equipment Bus Control |
Use Scenario: Interfacing SRAM or EPROM devices to microprocessors with shared address/data buses. IC Role / Device Role / Timing Role: Latches address information prior to memory access, freeing the bus for data transfer while maintaining valid address. Use Value: Enables full utilization of multiplexed bus architecture with guaranteed setup/hold times (10 ns su / 5 ns h @ 4.5 V). |
Use Scenario: Controlling signal routing and pattern generation in automated test equipment (ATE) channel cards. IC Role / Device Role / Timing Role: Provides precise, synchronized latching of stimulus vectors and capture of response data across multiple channels. Use Value: Delivers sub-20 ns timing accuracy and 3-state isolation between test channels, preventing cross-talk during parallel test execution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal transparent latch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT373DB,118 | TTL-compatible inputs (VIH = 2.0 V min); identical SO20 package and pinout. | Better interoperability with legacy 5 V TTL logic; slightly higher ICC (≤160 μA max). | Select when interfacing with older 74LS/74ALS families or where input threshold consistency across voltage rails is critical. |
| SN74HC373N | DIP-20 package; same electrical specs but through-hole mounting and wider temperature range (-40 °C to +85 °C only). | Suitable for prototyping, educational kits, or legacy board rework where SOIC footprint is unavailable. | Choose for hand-soldered development boards or replacement in existing DIP-based industrial controllers. |
Compared with 74HC373DB,118, the 74HCT373DB,118 offers improved input compatibility with 5 V TTL sources but trades minor power increase for robustness, while SN74HC373N sacrifices thermal rating and surface-mount efficiency for mechanical flexibility in non-production environments.
Availability
74HC373DB,118 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, microcontroller address latching, and memory interface buffering requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HC373DB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial and automotive applications.
The 74HC373 belongs to Nexperia's standard logic portfolio, engineered specifically for robust bus interface and data latching in noise-prone, thermally demanding embedded systems.
FAQ
What is the maximum clock frequency supported by the 74HC373DB,118?
The 74HC373DB,118 does not operate on a clock signal - it is a transparent latch controlled by level-sensitive LE and OE inputs. Its usable data rate is determined by propagation delay (15 ns typ @ 4.5 V) and setup/hold timing (10 ns su / 5 ns h), supporting reliable bus cycles up to approximately 33 MHz in well-designed layouts with matched trace lengths and proper termination.
Can the 74HC373DB,118 drive a 50 pF load at 6 V supply?
Yes. At VCC = 6.0 V, the device delivers 5.48 V VOH (min) at -7.8 mA and 0.26 V VOL (max) at +7.8 mA into a 50 pF capacitive load, meeting standard CMOS fanout requirements. Measured tpd is 12 ns typ, and transition time tt is 4 ns typ, ensuring clean signal edges without excessive ringing or overshoot when properly decoupled.
Is the GND pin (Pin 10) the only ground connection required?
Yes. Pin 10 is the sole dedicated ground terminal for the SO20 package. No secondary ground pins exist. To ensure noise immunity and thermal stability, connect Pin 10 to a low-impedance ground plane using short, wide traces and place a 100 nF ceramic decoupling capacitor between Pin 20 (VCC) and Pin 10 (GND) within 10 mm of the package.
Does the 74HC373DB,118 support hot-swap or live-insertion?
No. The device lacks built-in hot-swap protection circuitry such as slew-rate limiting or undervoltage lockout. Applying VCC before GND or inserting/removing while powered risks latch-up due to internal parasitic SCR activation. Always power-cycle the board before module insertion and follow Nexperia's recommended power sequencing: GND first, then VCC, then control signals.
74HC373DB,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HC
- Package/Case:
- 20-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 8:8
- Output Type:
- Tri-State
- Voltage - Supply:
- 2V ~ 6V
- Independent Circuits:
- 1
- Delay Time - Propagation:
- 12ns
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SSOP
74HC373DB,118 FAQ
1.How can I place an order for 74HC373DB,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC373DB,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC373DB,118 reliable?
The price and inventory of 74HC373DB,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC373DB,118 is usually 5 days.
3.What payment methods are accepted for 74HC373DB,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC373DB,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC373DB,118?
74HC373DB,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC373DB,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC373DB,118?
For technical support, including 74HC373DB,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC373DB,118 requirements.
6.How does Aetrix verify that 74HC373DB,118 is sourced from the original manufacturer or authorized distributors?
All 74HC373DB,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC373DB,118 meets industry standards.
7.What is the process for return or replacement of 74HC373DB,118?
All 74HC373DB,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC373DB,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC373DB,118 part is unused and in its original packaging.
Return procedure for 74HC373DB,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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