Nexperia USA Inc. 74HCT373BQ,115

Overview

74HCT373BQ,115 from Nexperia is an octal D-type transparent latch with 3-state outputs, designed for bus-oriented digital systems requiring data latching and controlled output isolation. It operates at 4.5 V to 5.5 V, features TTL-compatible inputs, supports -40 °C to +125 °C operation, and delivers 17 ns propagation delay (Dn→Qn) at VCC = 4.5 V with CL = 50 pF - used in microcontroller address/data bus buffering and memory interface control.

For engineers reviewing the 74HCT373BQ,115 datasheet, 74HCT373BQ,115 pinout, 74HCT373BQ,115 application, or 74HCT373BQ,115 equivalent, this device is selected for precise timing-critical bus hold functions where input compatibility with legacy TTL logic, low quiescent current (8 μA typical), and thermal-enhanced DHVQFN packaging are essential design requirements.

Technical Context

The 74HCT373BQ,115 implements eight independent D-latches with shared active-HIGH latch enable (LE) and active-LOW 3-state output enable (OE). Its TTL-level input thresholds (VIH = 2.0 V min, VIL = 0.8 V max at VCC = 5 V) ensure direct interfacing with 5 V TTL families without level-shifting. Latch transparency during LE HIGH and storage on LE HIGH-to-LOW transition provide deterministic edge-aligned sampling.

Each output drives up to ±6 mA at VOH ≥ 3.98 V and VOL ≤ 0.26 V (VCC = 4.5 V), while OE-controlled high-impedance state (IOZ ≤ ±0.5 μA) isolates the bus during contention or standby. Input clamp diodes allow safe interfacing to voltages exceeding VCC when used with current-limiting resistors.

Key Specifications

Pinout & Package

DHVQFN20 package (SOT764-1): 2.5 mm × 4.5 mm × 0.85 mm body, 20-terminal no-lead quad flat design with exposed thermal pad; optimized for high-density PCB layouts and improved thermal performance over SO20/TSSOP variants.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with 74HCT373PW,118, the 74HCT373BQ,115 offers superior thermal performance in high-density layouts; versus SN74HCT373PWR, it delivers lower power and faster timing - making it optimal for thermally constrained, timing-critical 5 V bus interfaces.

Availability

74HCT373BQ,115 is available at Aetrix Electronics and suitable for microcontroller bus buffering, memory address latching, and industrial I/O expansion requiring stable component supply across automotive, industrial control, and test equipment programs.

Supply support for 74HCT373BQ,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components - serving automotive, industrial, and consumer markets with AEC-Q100-qualified products and scalable manufacturing.

The 74HCT373BQ,115 belongs to Nexperia's 74HCT logic family, engineered for seamless interoperability with legacy TTL systems while delivering CMOS power efficiency and enhanced thermal reliability in modern surface-mount packages.

FAQ

What is the maximum clock frequency supported by the 74HCT373BQ,115?

The 74HCT373BQ,115 does not operate on a clock signal - it is an edge-triggered transparent latch controlled by the LE input. With a typical Dn→Qn propagation delay of 17 ns at VCC = 4.5 V, it supports reliable data capture at effective rates up to 25 MHz in synchronous bus systems, provided setup/hold times (tsu = 12 ns, th = 4 ns) are met relative to the LE edge.

Can the 74HCT373BQ,115 be used with a 3.3 V microcontroller?

No - the 74HCT373BQ,115 requires VCC = 4.5 V to 5.5 V and has TTL-level input thresholds (VIH = 2.0 V min). A 3.3 V MCU output may not reliably exceed VIH under worst-case conditions. For 3.3 V systems, use the 74LVC373 or 74ALVC373, which specify VIH = 2.0 V at VCC = 3.3 V and support 3.3 V supply operation.

Is the exposed thermal pad on the DHVQFN20 package required to be soldered?

The exposed pad (terminal 1 index area) has no electrical function and may remain unsoldered. If soldered, it must be either left electrically floating or connected to GND - no other connection is permitted. Proper thermal relief and solder paste stencil design are critical to avoid voiding and ensure mechanical reliability during reflow.

How does the 74HCT373BQ,115 handle input overvoltage conditions?

Inputs include integrated clamp diodes to VCC and GND. When interfacing to signals exceeding VCC, a series current-limiting resistor must be used to restrict IIK to ±20 mA maximum. For example, a 10 kΩ resistor limits current to <1 mA for a 12 V input at VCC = 5 V - enabling safe operation without external protection components.