NXP Semiconductors 74LVC162373ADGG,11

Overview

74LVC162373ADGG,11 from Nexperia is a 16-bit D-type transparent latch with integrated 30 Ω series termination resistors, 3-state outputs, and 5 V tolerant I/Os operating from 1.2 V to 3.6 V supply. It features dual independent 8-bit sections-each with dedicated latch enable (1LE/2LE) and output enable (1OE/2OE)-and supports mixed-voltage interfacing between 3.3 V and 5 V systems in high-speed data bus buffering applications.

For engineers reviewing the 74LVC162373ADGG,11 datasheet, 74LVC162373ADGG,11 pinout, 74LVC162373ADGG,11 application, or 74LVC162373ADGG,11 equivalent, this device delivers deterministic transparent latching with sub-8 ns propagation delay at 3.3 V, IOFF-enabled partial power-down protection, Schmitt-trigger inputs for noise immunity, and TSSOP48 packaging optimized for dense PCB layouts in industrial control and telecom backplane interfaces.

Technical Context

This latch implements two independent 8-bit transparent sections, each controlled by its own active-HIGH latch enable and active-LOW output enable. Data flows directly from D-inputs to Q-outputs when nLE is HIGH; on HIGH-to-LOW transition of nLE, the input state is captured and held regardless of subsequent D-input changes.

Outputs enter high-impedance state when nOE is HIGH, independent of latch state. The device integrates 30 Ω series termination resistors on all outputs to suppress signal reflections, supports 5.5 V-tolerant inputs even at 1.2 V VCC, and includes IOFF circuitry that disables outputs during power-down to prevent backflow current.

Key Specifications

Pinout & Package

TSSOP48 (SOT362-1) package: plastic thin shrink small outline, 48 leads, 6.1 mm body width, 0.5 mm pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with SN74LVC16373ADGGR, the 74LVC162373ADGG,11 reduces PCB component count via integrated termination; versus 74LVCH162373ADGG, it trades bus-hold capability for lower input leakage and marginally tighter AC specs - making it optimal for fixed-configuration, high-density interconnects.

Availability

74LVC162373ADGG,11 is available at Aetrix Electronics and suitable for industrial PLC backplane interfaces, automotive body control modules, telecom line card isolation, and test equipment digital pattern generation requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LVC162373ADGG,11 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVC162373ADGG,11 belongs to Nexperia's advanced LVC logic family, engineered for robust mixed-voltage interoperability, low-noise operation in dense PCB environments, and reliability in extended-temperature industrial deployments.

FAQ

What is the maximum clock frequency supported by the 74LVC162373ADGG,11?

The device does not operate on a clock signal-it is a transparent latch controlled by level-sensitive enable inputs. Its usable data rate is determined by propagation delay (≤5.9 ns at 3.3 V) and setup/hold times (≥2.0 ns su, ≥0.9 ns h), enabling reliable operation with input data edges up to ~100 MHz in well-terminated systems.

Can the 74LVC162373ADGG,11 be used with a 5 V microcontroller driving its inputs while powered at 3.3 V?

Yes. All inputs are 5.5 V tolerant regardless of VCC level (1.2 V to 3.6 V), allowing direct connection to 5 V logic without level shifters or clamping diodes. Output voltage swing remains rail-to-rail relative to the 3.3 V supply, maintaining compatibility with downstream 3.3 V receivers.

Does the 74LVC162373ADGG,11 support hot-swap or partial power-down operation?

Yes. Its IOFF circuitry actively disables outputs when VCC = 0 V, preventing backflow current from live I/O lines into the unpowered device. This feature is explicitly characterized per JEDEC JESD78 and supports safe insertion/removal in powered-backplane systems.

How does the integrated 30 Ω series termination improve signal integrity?

The 30 Ω resistors match typical PCB trace impedances (40–70 Ω) when combined with output driver impedance (~10–15 Ω), significantly reducing overshoot, undershoot, and ringing on unterminated or lightly loaded traces up to 15 cm. This eliminates the need for discrete resistors and associated layout area and parasitics.