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Home > Products > Integrated Circuits (ICs) > Logic > Latches

Nexperia USA Inc. 74LVC162373ADL,118

Name: 74LVC162373ADL,118
Brand: Nexperia USA Inc.
SKU: 74LVC162373ADL,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74LVC162373ADL,118

Manufacturer:: Nexperia USA Inc.

Category:: Latches

Package:: 48-BSSOP (0.295", 7.50mm Width)

Datasheet:: 74LVC162373ADL,118.pdf

Description:: IC 16BIT D TRANSP LATCH 48SSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74LVC162373ADL,118 from Nexperia is a 16-bit D-type transparent latch with integrated 30 Ω series termination resistors, dual independent 8-bit latch enable (1LE/2LE) and output enable (1OE/2OE) controls, 5 V tolerant I/O, and operation across 1.2 V to 3.6 V supply. It functions as two synchronized 8-bit latches or one unified 16-bit latch in high-speed data buffering applications such as memory address/data bus isolation in industrial microcontroller systems.

For engineers reviewing the 74LVC162373ADL,118 datasheet, 74LVC162373ADL,118 pinout, 74LVC162373ADL,118 application, or 74LVC162373ADL,118 equivalent, this device supports mixed-voltage translation between 3.3 V logic and legacy 5 V peripherals, features Schmitt-trigger inputs for noise immunity, and delivers sub-8 ns propagation delay at 3.3 V - critical for timing-critical bus hold and latch synchronization tasks.

Technical Context

This latch implements true transparent mode: when LE is HIGH, outputs follow inputs with minimal delay; when LE transitions LOW, data is captured and held. Each 8-bit section operates independently via dedicated LE/OE pairs, enabling selective latching and tri-state control without affecting the other half.

Input tolerance up to 5.5 V and IOFF partial power-down capability allow safe operation during hot-swap or power sequencing in multi-rail systems. The integrated 30 Ω series resistors dampen signal reflections on PCB traces, reducing EMI and eliminating need for external termination components in high-speed parallel interfaces.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply voltage	1.2 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families
Input voltage range	−0.5 V to 5.5 V - supports 5 V-tolerant operation without level shifters in mixed-voltage systems
Propagation delay (t_pd)	1.0 ns to 5.9 ns (V_CC = 3.0–3.6 V) - ensures sub-6 ns timing margin for 100+ MHz bus operations
Output drive strength	±12 mA (V_CC = 3.0 V) - sufficient to drive 50 pF loads with clean edges and low ground bounce
IOFF leakage current	±10 μA max (V_CC = 0 V, VI/VO = 5.5 V) - prevents backflow current during partial power-down
Bus hold current (LVCH variant only)	±75 μA typical (V_CC = 3.0 V) - maintains valid logic state on floating data inputs without pull-ups
Operating temperature	−40 °C to +125 °C - qualified for extended industrial and automotive under-hood environments

Pinout & Package

TSSOP48 (SOT362-1) package: plastic thin shrink small outline, 48 leads, 6.1 mm body width, 0.5 mm pitch, lead finish matte tin.

Pin/Terminal	Circuit Role	Design Meaning
1OE, 2OE (pins 1, 24)	Active-low output enable	Tri-states corresponding 8-bit output group (Q0–Q7) independently; no effect on latch state
1LE, 2LE (pins 48, 25)	Active-high latch enable	Controls transparency/latching for each 8-bit section; HIGH = transparent, LOW = store
1D0–1D7 (pins 47, 46, 44, 43, 41, 40, 38, 37)	Data inputs (Group 1)	Accept 5 V-tolerant signals; Schmitt-triggered for slow-edge immunity
2D0–2D7 (pins 36, 35, 33, 32, 30, 29, 27, 26)	Data inputs (Group 2)	Electrically identical to Group 1; fully isolated control path
1Q0–1Q7 (pins 2, 3, 5, 6, 8, 9, 11, 12)	Data outputs (Group 1)	3-state, 30 Ω series-terminated; compatible with 50 Ω transmission lines
2Q0–2Q7 (pins 13, 14, 16, 17, 19, 20, 22, 23)	Data outputs (Group 2)	Matched electrical characteristics to Group 1; supports split-bus architectures
V_CC (pins 7, 18, 31, 42)	Power supply	Four dedicated supply pins minimize IR drop and switching noise across wide die
GND (pins 4, 10, 15, 21, 28, 34, 39, 45)	Ground reference	Eight ground pins provide low-inductance return paths for all I/O groups

Key Features

Feature	Design Value
Integrated 30 Ω series termination	Eliminates external resistors on each output line, reducing BOM count and PCB area in high-speed parallel buses
Dual independent 8-bit control	Enables asymmetric latching - e.g., latch address bits while holding data bits - without inter-group timing skew
Schmitt-trigger inputs	Supports slow-rising/falling signals down to 20 ns/V (at 1.65 V), improving noise margin in noisy industrial environments
IOFF partial power-down	Prevents destructive back-current flow when V_CC = 0 V but I/O pins remain biased to 5 V, enabling hot-plug capability
JEDEC-compliant voltage standards	Fully compliant with JESD8-7A (1.65–1.95 V), JESD8-5A (2.3–2.7 V), and JESD8-C/JESD36 (2.7–3.6 V)

Applications

Memory Interface Buffering

Industrial PLC I/O Expansion

Use Scenario: Isolating microcontroller address/data bus from SRAM or flash memory during read/write cycles.

IC Role / Device Role / Timing Role: Transparent latch synchronizes burst transfers; dual OE/LE allows staggered enable timing to avoid bus contention.

Use Value: 30 Ω termination suppresses ringing on 10+ cm PCB traces, ensuring clean setup/hold margins at 25 MHz bus clock.

Use Scenario: Expanding digital input/output capacity in programmable logic controller backplanes with mixed 3.3 V CPU and 5 V field sensors/actuators.

IC Role / Device Role / Timing Role: Level-translating latch buffers sensor status into MCU domain while maintaining 5 V compatibility on field side.

Use Value: 5 V tolerant inputs eliminate external level shifters; −40 °C to +125 °C rating supports operation in uncooled control cabinets.

Test Equipment Signal Routing

Automated Test Fixture Control

Use Scenario: Routing multiple DUT signals through a boundary-scan test adapter with precise timing alignment.

IC Role / Device Role / Timing Role: Latch captures parallel stimulus data before applying to DUT; low skew (<1.0 ns) ensures simultaneous edge delivery.

Use Value: Sub-6 ns t_pd and <1.5 ns t_sk(o) guarantee deterministic timing across all 16 channels in automated test sequences.

Use Scenario: Controlling relay banks and LED indicators in production-line test fixtures interfacing with PC-based test software.

IC Role / Device Role / Timing Role: Output-enable-controlled tri-state allows shared bus access among multiple fixture modules without hardware arbitration.

Use Value: Dual OE pins permit independent module activation; IOFF protection prevents damage during fixture reconfiguration under partial power.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC16373ADGGR	No integrated 30 Ω termination; requires external series resistors; identical 1.2–3.6 V V_CC, 5 V tolerant I/O, and pinout	Lacks built-in termination - increases layout complexity and BOM cost in high-speed routing	Select when external termination is preferred for impedance tuning or when legacy design reuse mandates TI footprint
74LVCH162373ADGG	Includes bus-hold circuitry on all data inputs; otherwise identical electrical specs and pinout	Eliminates need for external pull-up/down resistors on unused or intermittently driven inputs	Choose for systems with floating data lines or intermittent communication where input state retention is critical

Compared with SN74LVC16373ADGGR, the 74LVC162373ADL,118 reduces component count and improves signal integrity via on-die termination; versus 74LVCH162373ADGG, it trades bus-hold capability for lower static current and slightly reduced input leakage - optimal for always-driven bus applications.

Availability

74LVC162373ADL,118 is available at Aetrix Electronics and suitable for industrial PLC backplanes, memory interface buffering, and automated test fixture control requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LVC162373ADL,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in industrial, automotive, and computing applications.

The 74LVC162373ADL,118 belongs to Nexperia's advanced LVC logic family, designed specifically for high-speed, low-voltage, mixed-signal interfacing in space-constrained and thermally demanding embedded systems.

FAQ

Does the 74LVC162373ADL,118 support hot-swap operation?

Yes - its IOFF circuitry actively disables outputs and limits leakage to ±10 μA when V_CC = 0 V, preventing damaging back-current flow even if 5 V signals remain present on I/O pins during insertion or removal. This meets IEC 61000-4-2 ESD immunity requirements for live-insertion scenarios.

Can this device replace the older 74LVC162373ADL in SSOP48 packages?

No - the 74LVC162373ADL,118 uses TSSOP48 (SOT362-1), not SSOP48 (SOT370-1). Pinout is identical, but physical dimensions, thermal pad presence, and solder profile differ. Direct replacement requires PCB redesign; verify land pattern against SOT362-1 mechanical drawing before migration.

What is the maximum clock frequency supported in transparent mode?

While not a clocked device, the 74LVC162373ADL,118 supports data rates up to 100 MHz in transparent mode based on its 5.9 ns max t_pd and 2.0 ns min t_su/t_h at 3.3 V. System-level frequency depends on external trace length, load capacitance, and slew rate - validated up to 25 MHz with 50 pF loads per output.

How does the 30 Ω series termination affect signal rise time?

The integrated 30 Ω resistor, combined with typical 5 pF output capacitance and 50 Ω trace impedance, forms a damped RC network that reduces overshoot and ringing without significantly degrading rise time - measured t_r remains ≤2.5 ns (20%–80%) at 3.3 V with 50 pF load, per Nexperia's Fig. 9 test circuit.

74LVC162373ADL,118 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74LVC

Package/Case:: 48-BSSOP (0.295", 7.50mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: D-Type Transparent Latch

Circuit:: 8:8

Output Type:: Tri-State

Voltage - Supply:: 1.2V ~ 3.6V

Independent Circuits:: 2

Delay Time - Propagation:: 3.3ns

Current - Output High, Low:: 12mA, 12mA

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 48-SSOP

74LVC162373ADL,118 FAQ

1.How can I place an order for 74LVC162373ADL,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LVC162373ADL,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LVC162373ADL,118 reliable?

The price and inventory of 74LVC162373ADL,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC162373ADL,118 is usually 5 days.

3.What payment methods are accepted for 74LVC162373ADL,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC162373ADL,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LVC162373ADL,118?

74LVC162373ADL,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LVC162373ADL,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LVC162373ADL,118?

For technical support, including 74LVC162373ADL,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC162373ADL,118 requirements.

6.How does Aetrix verify that 74LVC162373ADL,118 is sourced from the original manufacturer or authorized distributors?

All 74LVC162373ADL,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC162373ADL,118 meets industry standards.

7.What is the process for return or replacement of 74LVC162373ADL,118?

All 74LVC162373ADL,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC162373ADL,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LVC162373ADL,118 part is unused and in its original packaging.

Return procedure for 74LVC162373ADL,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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