Nexperia USA Inc. 74LVC16373ADGG,112

Overview

74LVC16373ADGG,112 from Nexperia is a 16-bit D-type transparent latch with 3-state outputs, dual latch enable (1LE/2LE) and dual output enable (1OE/2OE) control per 8-bit section, 5 V tolerant I/O (up to 5.5 V), 1.2 V to 3.6 V supply operation, and bus hold on data inputs - used in high-density address/data latching for industrial microcontroller buses and FPGA I/O expansion.

For engineers reviewing the 74LVC16373ADGG,112 datasheet, 74LVC16373ADGG,112 pinout, 74LVC16373ADGG,112 application, or 74LVC16373ADGG,112 equivalent, this device supports mixed-voltage interfacing between 3.3 V logic and legacy 5 V peripherals, enables partial power-down via IOFF, and provides Schmitt-trigger input noise immunity for slow-rising control signals in noisy industrial environments.

Technical Context

This latch operates in transparent mode when LE is HIGH (output follows input), stores data on HIGH-to-LOW LE transition, and enters high-impedance state when OE is LOW - independent of latch state. Its dual-section architecture allows independent control of two 8-bit channels for segmented bus management.

IOFF circuitry disables outputs during power-down to prevent backflow current; bus hold eliminates external pull-ups on unused D-inputs; Schmitt-trigger inputs tolerate >10 ns/V input slew rates at VCC ≥ 2.7 V, supporting reliable operation with RC-filtered or long-trace signals.

Key Specifications

Pinout & Package

TSSOP48 package (SOT362-1), 48-pin plastic thin shrink small outline, 6.1 mm body width, 0.5 mm lead pitch - optimized for high-density PCB layouts with low thermal resistance (12.2 mW/K derating above 109 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with 74LVCH16373ADGG, the 74LVC16373ADGG omits bus hold to reduce cost and static current, while SN74LVC16373ADGGR trades bus hold for TI-specific qualification - making the Nexperia part optimal for new designs prioritizing cost, noise immunity, and mixed-voltage robustness.

Availability

74LVC16373ADGG,112 is available at Aetrix Electronics and suitable for industrial PLC backplanes, FPGA I/O expansion modules, automotive body control units, and automated test equipment requiring stable component supply across extended temperature and mixed-voltage operation.

Supply support for 74LVC16373ADGG,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVC16373A belongs to Nexperia's advanced LVC logic family, engineered for ultra-low power, wide supply range, and robust mixed-voltage interoperability in space- and power-constrained embedded systems.

FAQ

Can 74LVC16373ADGG,112 operate with a 1.2 V supply?

Yes - it is fully specified from 1.2 V to 3.6 V. At 1.2 V, propagation delay increases to 12 ns (D→Q), VIH drops to 1.08 V, and VOL rises to 0.12 V, enabling compatibility with ultra-low-power microcontrollers like the MSP430FR series in battery-operated sensors.

Does this device support hot insertion into a live 5 V bus?

Yes - its 5.5 V input tolerance and IOFF circuitry allow safe connection to an active 5 V bus while VCC is unpowered. Output leakage remains ≤±10 μA at VCC = 0 V and VI = 5.5 V, preventing backfeed into the host system.

How does bus hold function differ between 74LVC16373A and 74LVCH16373A?

Only the 'H' variant (74LVCH16373A) includes bus hold on data inputs. The standard 74LVC16373A lacks this feature - meaning unused D-inputs must be externally terminated to avoid floating states and potential shoot-through current in downstream drivers.

What is the maximum clock rate supported for transparent latching?

It does not use a clock - latching is controlled by level-sensitive LE inputs. Maximum data throughput is limited by propagation delay (≤5.5 ns at 3.3 V) and set-up/hold times (2.0 ns / +0.9 ns), supporting reliable operation up to ~100 MHz in synchronous bus architectures with proper timing margins.