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Nexperia USA Inc. 74LVC16373ADGG,118
- Part No.:
- 74LVC16373ADGG,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Latches
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
74LVC16373ADGG,118.pdf
- Description:
- IC TRANS D-TYP LATCH 3ST 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:6,608
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Product details
Overview
74LVC16373ADGG,118 from Nexperia is a 16-bit D-type transparent latch with 3-state outputs, dual latch enables (1LE/2LE) and dual output enables (1OE/2OE), operating from 1.2 V to 3.6 V supply, with 5.5 V tolerant inputs/outputs, and specified for -40 °C to +125 °C. It functions as two independent 8-bit latches or one unified 16-bit latch in bus-hold–enabled data buffering applications.
For engineers reviewing the 74LVC16373ADGG,118 datasheet, 74LVC16373ADGG,118 pinout, 74LVC16373ADGG,118 application, or 74LVC16373ADGG,118 equivalent, key selection considerations include 5 V tolerance in mixed-voltage systems, IOFF partial power-down capability, Schmitt-trigger input noise immunity, and TSSOP48 package compatibility with high-density PCB layouts.
Technical Context
This device implements dual 8-bit transparent latch architecture with independent control of latch and output enable per byte. Each latch section responds to active-HIGH LE and active-LOW OE signals, enabling precise timing control in address/data bus isolation and level translation scenarios.
It integrates bus hold on all data inputs (per 74LVCH variant), IOFF circuitry for backflow current suppression during partial power-down, and Schmitt-trigger inputs for robust operation with slow-rising signals - all compliant with JEDEC JESD8-7A, JESD8-5A, and JESD8-C standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 1.2 V to 3.6 V - supports low-power 1.2 V logic domains and interoperability with 3.3 V systems |
| Input voltage tolerance | Up to 5.5 V - enables direct interfacing with 5 V TTL/CMOS sources without external level shifters |
| Propagation delay (D→Q) | 1.0 ns (min) to 5.5 ns (max) at VCC = 3.0–3.6 V - ensures sub-6 ns timing margin for 100+ MHz bus operations |
| IOFF leakage current | ±10 μA max at VCC = 0 V, VI/VO = 5.5 V - prevents damaging backflow during hot-swap or partial power-down |
| Bus hold current | ±75 μA at VCC = 3.0 V - eliminates need for external pull-up/down resistors on unused data inputs |
| Operating temperature | -40 °C to +125 °C - qualified for automotive under-hood and industrial control environments |
| ESD protection | HBM >2000 V, CDM >1000 V - meets IEC 61000-4-2 Level 3 system-level robustness requirements |
Pinout & Package
TSSOP48 plastic thin shrink small outline package (SOT362-1), 48-pin, body width 6.1 mm, lead pitch 0.5 mm, 1.2 mm max height - optimized for automated SMT assembly and thermal performance in space-constrained designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE (pins 1, 24) | Active-low output enable | Controls 3-state output drivers for respective 8-bit sections; independent of latch state |
| 1LE, 2LE (pins 48, 25) | Active-high latch enable | Enables transparency (pass-through) when HIGH; captures and holds data on HIGH-to-LOW transition |
| 1D0–1D7 (pins 47, 46, 44, 43, 41, 40, 38, 37) | Data inputs (byte 1) | Accept 1.2–5.5 V logic levels; include integrated bus hold for floating-input immunity |
| 2D0–2D7 (pins 36, 35, 33, 32, 30, 29, 27, 26) | Data inputs (byte 2) | Same electrical behavior as 1Dx; electrically isolated but share same VCC/GND rails |
| 1Q0–1Q7 (pins 2, 3, 5, 6, 8, 9, 11, 12) | Data outputs (byte 1) | 3-state CMOS outputs with 5.5 V tolerance; driven only when corresponding 1OE = LOW |
| 2Q0–2Q7 (pins 13, 14, 16, 17, 19, 20, 22, 23) | Data outputs (byte 2) | Independent 3-state control via 2OE; supports byte-wise bus isolation |
| VCC (pins 7, 18, 31, 42) | Power supply | Four dedicated supply pins minimize IR drop and ground bounce in high-speed switching |
| GND (pins 4, 10, 15, 21, 28, 34, 39, 45) | Ground reference | Eight ground pins provide low-inductance return paths for simultaneous switching outputs |
Key Features
| Feature | Design Value |
|---|---|
| Dual 8-bit latch architecture | Enables independent control of two data bytes - critical for segmented address/data buses in microcontroller peripherals |
| 5.5 V tolerant I/O | Allows direct connection to legacy 5 V logic without external translators - reduces BOM count and layout complexity |
| IOFF partial power-down | Disables outputs and blocks backflow current when VCC = 0 V - essential for hot-plug and power-gating systems |
| Schmitt-trigger inputs | Provides hysteresis (typically 0.3–0.5 V) - rejects noise on slow-rising clock or control signals in noisy industrial environments |
| Bus hold on data inputs | Maintains valid logic state on un-driven inputs - eliminates external pull resistors and saves PCB area in high-pin-count designs |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
|
Use Scenario: Buffering and isolating 16-bit parallel data between MCU and peripheral I/O expanders in programmable logic controllers. IC Role / Device Role / Timing Role: Acts as a synchronized data capture interface between 3.3 V MCU and 5 V sensor/actuator subsystems. Use Value: Dual-byte control allows independent gating of address and data lanes, reducing bus contention and improving scan-cycle determinism. |
Use Scenario: Level-shifting and latching door/window status signals from 5 V analog front-ends to 3.3 V CAN microcontrollers. IC Role / Device Role / Timing Role: Provides glitch-free signal capture during vehicle power sequencing using IOFF and Schmitt-trigger inputs. Use Value: 5.5 V tolerance and -40 °C to +125 °C rating ensure reliable operation across battery voltage transients and under-hood thermal extremes. |
| Server Memory Subsystem | Test Equipment Digital Pattern Generator |
|
Use Scenario: Isolating DDR memory controller address/command bus from DIMM presence detection logic in enterprise servers. IC Role / Device Role / Timing Role: Transparent latch synchronizes asynchronous presence signals to memory controller clock domain. Use Value: Sub-6 ns propagation delay and low skew (<1.5 ns) preserve setup/hold timing margins in high-speed memory interfaces. |
Use Scenario: Capturing and holding digital stimulus patterns from FPGA-based pattern generators before driving DUT test vectors. IC Role / Device Role / Timing Role: Functions as a static pattern register with independent byte enables for multi-channel test vector staging. Use Value: Bus hold eliminates floating inputs during pattern reconfiguration, preventing spurious transitions on test channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit transparent latch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVCH16373ADGG | Includes bus hold on all data inputs; identical pinout, timing, and voltage specs | Preferred where unused inputs may float (e.g., configurable I/O modules) | Select when bus hold is required; otherwise 74LVC16373ADGG offers identical core functionality at lower cost |
| SN74LVC16373APAG | TSSOP48 package, same logic function, but TI version has higher ICC (80 μA vs 20 μA max) and no IOFF | Lacks partial power-down support - unsuitable for hot-swap or dynamic power management | Use only if IOFF and ultra-low standby current are not required; verify thermal derating for 125 °C operation |
Compared with 74LVCH16373ADGG, this part omits bus hold but retains identical timing, voltage tolerance, and IOFF - making it optimal for cost-sensitive, fully driven-bus applications. Versus SN74LVC16373APAG, it delivers superior power-down safety and lower quiescent current for automotive and industrial use.
Availability
74LVC16373ADGG,118 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, and server memory subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LVC16373ADGG,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for automotive, industrial, and computing markets.
The 74LVC family targets low-voltage, high-speed logic interfacing with emphasis on mixed-supply compatibility, robust ESD performance, and extended temperature operation - directly supporting next-generation embedded control architectures.
FAQ
Does 74LVC16373ADGG,118 support true 5 V operation?
No - its VCC must be 1.2 V to 3.6 V, but inputs and outputs tolerate up to 5.5 V. This allows connection to 5 V signal sources while powered from 3.3 V or lower, eliminating external level shifters in mixed-voltage systems.
How does IOFF protect the device during partial power-down?
When VCC = 0 V, the IOFF circuit disables all output drivers and blocks current flow between powered and unpowered sections - preventing backfeed that could damage upstream 5 V drivers or cause system latch-up in hot-swap applications.
What is the functional difference between 1LE/2LE and 1OE/2OE?
1LE/2LE control data capture: HIGH enables transparency, LOW latches current input values. 1OE/2OE control output drivers: LOW enables outputs, HIGH forces high-impedance - allowing independent data storage and bus release per byte.
Can this device replace 74LVC162373 in existing designs?
No - 74LVC162373 is a 16-bit latch with different pinout (separate GND/VCC per 8-bit section) and no bus hold. 74LVC16373ADGG,118 shares pin compatibility only with other 74LVC16373A variants (e.g., DGV, DL) and requires PCB layout verification for TSSOP48 footprint.
74LVC16373ADGG,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 8:8
- Output Type:
- Tri-State
- Voltage - Supply:
- 1.65V ~ 3.6V
- Independent Circuits:
- 2
- Delay Time - Propagation:
- 1ns
- Current - Output High, Low:
- 24mA, 24mA
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-TSSOP
74LVC16373ADGG,118 FAQ
1.How can I place an order for 74LVC16373ADGG,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC16373ADGG,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC16373ADGG,118 reliable?
The price and inventory of 74LVC16373ADGG,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC16373ADGG,118 is usually 5 days.
3.What payment methods are accepted for 74LVC16373ADGG,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC16373ADGG,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC16373ADGG,118?
74LVC16373ADGG,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC16373ADGG,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC16373ADGG,118?
For technical support, including 74LVC16373ADGG,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC16373ADGG,118 requirements.
6.How does Aetrix verify that 74LVC16373ADGG,118 is sourced from the original manufacturer or authorized distributors?
All 74LVC16373ADGG,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC16373ADGG,118 meets industry standards.
7.What is the process for return or replacement of 74LVC16373ADGG,118?
All 74LVC16373ADGG,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC16373ADGG,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC16373ADGG,118 part is unused and in its original packaging.
Return procedure for 74LVC16373ADGG,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC16373ADGG,118 Tags
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