Nexperia USA Inc. 74LVC16373ADGG,518

Overview

74LVC16373ADGG,518 from Nexperia is a 16-bit D-type transparent latch with 3-state outputs, dual 8-bit latch enable (1LE/2LE) and output enable (1OE/2OE) controls, 5 V tolerant I/O (up to 5.5 V), 1.2 V to 3.6 V supply range, and bus hold on data inputs - used in high-density address/data bus latching for industrial microcontroller interfaces and mixed-voltage memory expansion systems.

For engineers reviewing the 74LVC16373ADGG,518 datasheet, 74LVC16373ADGG,518 pinout, 74LVC16373ADGG,518 application, or 74LVC16373ADGG,518 equivalent, key selection criteria include 5 V tolerance in 3.3 V domains, IOFF-enabled partial power-down operation, Schmitt-trigger input noise immunity, TSSOP48 thermal performance at +125 °C, and bus hold elimination of external pull-ups.

Technical Context

This device implements two independent 8-bit transparent latch sections, each with separate LE and OE control, enabling flexible partitioning of 16-bit buses without inter-section timing coupling. Its IOFF circuitry disables outputs during power-down to prevent backflow current, satisfying JEDEC JESD78 Class II latch-up immunity requirements.

Schmitt-trigger inputs provide hysteresis (typ. 0.3 V at VCC = 3.3 V), supporting slow-rising signals down to 10 ns/V slew rate, while bus hold sustains logic states at data inputs (IBHL = −60 μA at VI = 0.8 V, VCC = 3.0 V), eliminating external biasing in floating-bus scenarios.

Key Specifications

Pinout & Package

TSSOP48 plastic thin shrink small outline package (SOT362-1), 48 leads, body width 6.1 mm, lead pitch 0.5 mm, exposed pad not present, JEDEC MO-153 compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with 74LVCH16373ADGG, the 74LVC16373ADGG omits bus hold but retains identical timing, voltage tolerance, and IOFF - making it optimal for cost-sensitive, fully driven-bus designs. SN74LVC16373APAG requires additional external components and offers weaker noise immunity, limiting its suitability in industrial settings.

Availability

74LVC16373ADGG,518 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, embedded memory interfaces, and FPGA configuration bridges requiring stable component supply across extended temperature ranges and mixed-voltage operation.

Supply support for 74LVC16373ADGG,518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, with leadership in automotive-grade and industrial-grade discrete and logic devices.

The 74LVC16373A belongs to Nexperia's LVC logic family, engineered for low-voltage, high-speed, mixed-signal interface applications in automotive, industrial, and computing systems demanding robustness, low power, and wide supply flexibility.

FAQ

What is the maximum operating frequency supported by the 74LVC16373ADGG,518?

The device does not specify a maximum clock frequency, as it is a transparent latch-not a clocked register-but its propagation delay (D→Q) is 1.0–5.5 ns at VCC = 3.0–3.6 V. This enables reliable operation in systems with bus toggle rates up to 100 MHz, assuming setup/hold times (tsu = 2.0 ns, th = +0.9 ns) are met. Timing is governed by LE edge transitions, not periodic clocks.

Can the 74LVC16373ADGG,518 be used in a 5 V-only system?

No-its VCC must be 1.2–3.6 V; however, its inputs and outputs tolerate up to 5.5 V regardless of VCC. In a 5 V system, it must be powered from a 3.3 V rail (or lower), while interfacing directly with 5 V logic signals. This makes it ideal for translating between 5 V peripherals and 3.3 V controllers, but it cannot replace a true 5 V logic device like the 74HC573.

Does the 74LVC16373ADGG,518 support hot-swap or partial power-down?

Yes-its IOFF circuitry actively disables outputs when VCC = 0 V, limiting power-off leakage to ±10 μA maximum even with 5.5 V applied to I/O pins. This prevents backflow current and latch-up during live insertion/removal in modular systems such as industrial backplanes or telecom line cards.

How does bus hold function differ between 74LVC16373ADGG and 74LVCH16373ADGG?

The 74LVC16373ADGG does not include bus hold; only the 'H' variant (74LVCH16373ADGG) provides this feature on data inputs. Bus hold sustains logic states via internal feedback (IBHL = −60 μA at VI = 0.8 V), eliminating external pull-ups. The base LVC version requires external termination if inputs may float, making the 'H' variant preferable for configurable or sparse-bus applications.