Nexperia USA Inc. 74LVC16373ADGVJ

Overview

74LVC16373ADGV from Nexperia is a 16-bit D-type transparent latch with 3-state outputs, dual latch enable (1LE/2LE) and dual output enable (1OE/2OE), 5 V tolerant I/O, 1.2 V to 3.6 V supply range, and bus hold on data inputs. It operates as two independent 8-bit latches or one unified 16-bit latch in mixed-voltage digital systems such as industrial PLC I/O modules.

For engineers reviewing the 74LVC16373ADGV datasheet, 74LVC16373ADGV pinout, 74LVC16373ADGV application, or 74LVC16373ADGV equivalent, key selection criteria include 5 V tolerance for legacy interface bridging, IOFF-enabled partial power-down capability, Schmitt-trigger input noise immunity, and TVSOP48 package suitability for high-density PCB layouts.

Technical Context

This device implements two independent 8-bit transparent latch sections, each controlled by dedicated LE and OE signals. Its dual-section architecture enables selective latching and tri-state control per byte without cross-talk or timing interference between halves.

Inputs feature Schmitt-trigger action for robust handling of slow-rising signals, and bus hold circuitry eliminates external pull-ups on unused data inputs. The IOFF circuit actively disables outputs during power-down, preventing backflow current when VCC = 0 V while inputs remain at 5.5 V.

Key Specifications

Pinout & Package

74LVC16373ADGV uses the SOT480-1 (TVSOP48) package: 48-pin plastic thin shrink small outline, 4.4 mm body width, 0.4 mm lead pitch, and exposed pad not present. Pin numbering follows standard counter-clockwise layout with pin 1 index marker at top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with 74LVCH16373ADGV, the 74LVC16373ADGV omits bus hold-reducing input leakage but requiring external termination on floating lines; versus SN74LVC16373APAG, it offers finer pitch and lower profile for space-constrained layouts but with tighter thermal limits above 60 °C.

Availability

74LVC16373ADGV is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, FPGA configuration interfaces, and test equipment digital pattern generators requiring stable component supply across extended temperature ranges.

Supply support for 74LVC16373ADGV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial and automotive applications.

The 74LVC/LVCH logic family targets voltage-flexible, low-power digital interfacing-designed specifically for bridging mixed-supply domains while maintaining signal integrity and robustness in harsh environments.

FAQ

What is the maximum input voltage the 74LVC16373ADGV can tolerate?

The 74LVC16373ADGV accepts input voltages up to 5.5 V regardless of VCC level, enabling direct connection to 5 V TTL or CMOS sources without level-shifting circuitry. This overvoltage tolerance is guaranteed across the full operating temperature range (−40 °C to +125 °C) and applies to all data and control inputs (Dn, LE, OE).

Does the 74LVC16373ADGV support partial power-down mode?

Yes-the device integrates IOFF circuitry that automatically disables outputs and limits leakage to ±10 μA when VCC = 0 V, even with inputs held at 5.5 V. This prevents back-current flow in hot-swap or modular power architectures where subsystems may be powered independently.

How does the dual latch enable (1LE/2LE) improve system design flexibility?

1LE and 2LE allow independent latching of two 8-bit data groups-enabling time-staggered capture (e.g., high-byte then low-byte), selective update of subsets of I/O, or isolation between functional blocks. Each section operates transparently when its LE is HIGH and holds data when LOW, with no interaction between sections.

Is bus hold functionality present on the 74LVC16373ADGV?

No-bus hold is exclusive to the 74LVCH16373A variant. The 74LVC16373ADGV lacks internal bus hold circuitry on data inputs, meaning unused D-lines must be externally terminated with pull-up or pull-down resistors to prevent floating states and potential noise-induced glitches.