Nexperia USA Inc. 74LVC16373ADL,112

Overview

74LVC16373ADL,112 from Nexperia is a 16-bit D-type transparent latch with dual 8-bit latch enable (1LE/2LE) and output enable (1OE/2OE) controls, 5 V tolerant I/O, 3-state outputs, and bus hold on data inputs. It operates from 1.2 V to 3.6 V supply, supports mixed-voltage interfacing between 3.3 V and 5 V systems, and is specified for -40 °C to +125 °C. It serves as a bidirectional data latching interface in high-density memory address/data bus buffering.

For engineers reviewing the 74LVC16373ADL,112 datasheet, 74LVC16373ADL,112 pinout, 74LVC16373ADL,112 application, or 74LVC16373ADL,112 equivalent, key selection criteria include 5 V tolerance on all I/O pins, IOFF partial power-down support, Schmitt-trigger input noise immunity, bus hold functionality eliminating external pull-ups, and TSSOP48 package compatibility with high-pin-count PCB layouts.

Technical Context

This device implements two independent 8-bit transparent latches sharing a common 48-pin TSSOP package. Each latch section features separate active-HIGH latch enable (nLE) and active-LOW output enable (nOE), enabling selective capture and tri-state control of 8-bit data channels without cross-talk.

Its IOFF circuitry disables outputs during power-down to prevent backflow current, while Schmitt-trigger inputs tolerate slow-rising signals and ensure robust noise rejection. Bus hold on all data inputs maintains valid logic states when inputs float-critical for hot-swap and unpopulated bus segments.

Key Specifications

Pinout & Package

74LVC16373ADL,112 is housed in a plastic thin shrink small outline package (TSSOP48) per SOT362-1 standard: 48 leads, 6.1 mm body width, 0.5 mm lead pitch, and exposed thermal pad not present. Pin numbering follows standard counter-clockwise layout starting from pin 1 (1OE) at top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with 74LVCH16373ADL,112, the original part lacks bus hold - requiring external termination on floating inputs - while SN74LVC16373APAG trades extended temperature range and IOFF robustness for lower unit cost in benign environments.

Availability

74LVC16373ADL,112 is available at Aetrix Electronics and suitable for memory interface buffering, industrial PLC I/O expansion, and automotive ADAS sensor hub applications requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LVC16373ADL,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in automotive, industrial, and consumer electronics.

The 74LVC/LVCH logic family targets low-voltage, high-speed digital interfacing with emphasis on voltage translation, bus isolation, and power-aware design for modern embedded systems.

FAQ

Does 74LVC16373ADL,112 support partial power-down when VCC is disconnected?

Yes. Its IOFF circuitry activates when VCC = 0 V, forcing all outputs into high-impedance state regardless of OE/LE logic levels. This prevents back-current flow from live 5 V buses into the unpowered device, satisfying IEC 61000-4-2 and automotive power sequencing requirements.

Can 74LVC16373ADL,112 drive 50 pF loads at 3.3 V while meeting tpd ≤ 5 ns?

Yes. At VCC = 3.3 V and CL = 50 pF, typical propagation delay (D→Q) is 2.4 ns with maximum 4.4 ns across -40 °C to +125 °C - well within 5 ns margin. Test conditions match JEDEC-standard load and termination per datasheet Figure 9 and Table 9.

What is the function of the Schmitt-trigger inputs on this latch?

Schmitt-trigger inputs provide hysteresis (≥0.3 V at VCC = 3.3 V) to reject noise on slow-rising/falling control signals such as manual switches, long traces, or optocoupler outputs. This eliminates false triggering without external RC filtering or debouncing firmware.

How does bus hold operate on 74LVC16373ADL,112, and is it enabled by default?

Bus hold is intrinsic to all data inputs (1D0–1D7, 2D0–2D7) and requires no configuration. It sources/sinks ±60 μA at VCC = 3.0 V to maintain the last valid logic state when inputs float - verified per datasheet Table 6 IBHL/IBHH parameters and Figure 4 circuit diagram.