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Nexperia USA Inc. 74LVC16373ADL,118
- Part No.:
- 74LVC16373ADL,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Latches
- Package:
- 48-BSSOP (0.295", 7.50mm Width)
- Datasheet:
-
74LVC16373ADL,118.pdf
- Description:
- IC 16BIT D TRANSP LATCH 48SSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,546
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Product details
Overview
74LVC16373ADL,118 from Nexperia is a 16-bit D-type transparent latch with 3-state outputs, dual latch enables (1LE/2LE) and dual output enables (1OE/2OE), operating from 1.2 V to 3.6 V supply, with 5.5 V tolerant inputs/outputs, and specified for -40 °C to +125 °C. It functions as two independent 8-bit latches or one unified 16-bit latch in bus-hold-equipped data paths of industrial microcontroller interfaces.
For engineers reviewing the 74LVC16373ADL,118 datasheet, 74LVC16373ADL,118 pinout, 74LVC16373ADL,118 application, or 74LVC16373ADL,118 equivalent, key selection criteria include its 5.5 V input tolerance enabling mixed-voltage level translation, IOFF partial power-down capability for hot-swap systems, and bus-hold on all data inputs eliminating external pull-ups in floating-bus scenarios.
Technical Context
This device implements two independent 8-bit transparent latch sections, each controlled by dedicated LE and OE signals, allowing selective latching and tri-stating of half the bus without affecting the other. Its Schmitt-trigger inputs tolerate slow-rising signals, while the IOFF circuit disables outputs during power-down to prevent backflow current.
Bus hold functionality-present on all data inputs-maintains valid logic states when inputs float, reducing system-level component count. The latch operates in transparent mode when LE is HIGH and stores data on the HIGH-to-LOW transition, with output enable independent of latch state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 1.2 V to 3.6 V - supports low-power 1.2 V logic domains and interoperability with 3.3 V systems |
| Input voltage tolerance | Up to 5.5 V - enables direct interfacing with 5 V peripherals without level shifters |
| Propagation delay (D→Q) | 1.0 ns to 4.4 ns at VCC = 3.0–3.6 V - ensures timing-critical bus synchronization in high-speed control paths |
| IOFF leakage | ±10 μA max at VCC = 0 V, VI/VO = 5.5 V - guarantees safe partial power-down in multi-rail systems |
| Bus hold current | ±60 μA to ±75 μA at VCC = 3.0 V - actively sustains logic states on unused inputs without external resistors |
| Operating temperature | -40 °C to +125 °C - qualified for under-hood automotive and industrial motor-control environments |
| ESD protection | HBM >2000 V, CDM >1000 V - robust handling in automated PCB assembly and field service |
Pinout & Package
TSSOP48 package (SOT362-1), plastic thin shrink small outline, 48 leads, body width 6.1 mm, lead pitch 0.5 mm, 8 exposed ground pins and 4 VCC pins for low-noise operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE (Pins 1, 24) | Active-low 3-state output enable | Independently disables 8-bit output groups; does not affect internal latch state |
| 1LE, 2LE (Pins 48, 25) | Active-high latch enable | Controls transparency/storage per 8-bit section; data captured on HIGH→LOW edge |
| 1D0–1D7 (Pins 47, 46, 44, 43, 41, 40, 38, 37) | Data inputs (Group 1) | Bus-hold enabled; tolerate 5.5 V inputs while powered from 1.2–3.6 V |
| 2D0–2D7 (Pins 36, 35, 33, 32, 30, 29, 27, 26) | Data inputs (Group 2) | Same bus-hold and overvoltage tolerance as Group 1 |
| 1Q0–1Q7 (Pins 2, 3, 5, 6, 8, 9, 11, 12) | Data outputs (Group 1) | 3-state capable; drive strength up to 24 mA at 3.0 V |
| 2Q0–2Q7 (Pins 13, 14, 16, 17, 19, 20, 22, 23) | Data outputs (Group 2) | Independent 3-state control via 2OE; matched timing to Group 1 |
| VCC (Pins 7, 18, 31, 42) | Power supply | Four distributed supply pins minimize IR drop and ground bounce in high-speed switching |
| GND (Pins 4, 10, 15, 21, 28, 34, 39, 45) | Ground reference | Eight ground pins provide low-inductance return paths for all I/O groups |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent 8-bit latch control | Enables selective data capture and isolation across two sub-buses without cross-talk |
| 5.5 V tolerant I/O on 1.2–3.6 V supply | Eliminates external level translators in mixed-voltage MCU-peripheral interconnects |
| IOFF partial power-down | Prevents damaging back-current when VCC = 0 V but I/O lines remain active at 5 V |
| Integrated bus hold on all data inputs | Removes need for 16 external pull-up/pull-down resistors in unconnected or shared-bus configurations |
| Schmitt-trigger inputs | Accepts slow-rising signals (e.g., from mechanical switches or long traces) without oscillation |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
|
Use Scenario: Expanding GPIO count of an ARM Cortex-M7 MCU driving solenoids, relays, and sensors across multiple CAN nodes. IC Role / Device Role / Timing Role: Acts as bidirectional data latch between MCU parallel bus and isolated peripheral driver ICs, synchronizing write strobes and read acknowledges. Use Value: Bus hold prevents floating inputs during hot-plug module insertion; 5.5 V tolerance allows direct connection to 5 V sensor outputs without level-shifting components. |
Use Scenario: Interfacing a 3.3 V domain microcontroller to legacy 5 V dashboard displays and lighting drivers. IC Role / Device Role / Timing Role: Transparent latch buffers display update data during MCU interrupt latency; 3-state outputs isolate bus during firmware updates. Use Value: IOFF protection ensures no backfeed into MCU during ignition-off battery drain modes; -40 °C to +125 °C rating meets AEC-Q100 Grade 1 requirements. |
| Test Equipment Digital Pattern Generator | Medical Imaging Data Acquisition |
|
Use Scenario: Generating precise digital stimulus patterns for ASIC validation using FPGA-controlled parallel buses. IC Role / Device Role / Timing Role: Latches pattern words from FPGA fabric before applying to DUT; dual LE/OE allows staggered word loading and synchronized release. Use Value: Sub-5 ns propagation delay ensures nanosecond-level timing accuracy; TSSOP48 package supports high-density PCB layout with minimal trace skew. |
Use Scenario: Capturing parallel ADC output streams from multi-channel ultrasound front-ends before serialization. IC Role / Device Role / Timing Role: Holds sampled pixel data stable during DMA transfer to memory; 3-state outputs decouple ADC bus during calibration cycles. Use Value: Low 0.1 μA typical ICC at 3.3 V reduces thermal load in sealed imaging enclosures; ESD robustness protects against handling discharge during field servicing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit transparent latch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVCH16373ADL,118 | Includes bus hold on all data inputs; otherwise identical electrical specs and pinout | Preferred where unused data lines require guaranteed logic state without external biasing | Select this variant if board layout lacks space or BOM budget for 16 pull-up resistors |
| SN74ALVCH16373DGGR | TI part; wider VCC range (1.65–3.6 V); higher drive (±24 mA); same 48-pin TSSOP | Valid for 1.65 V minimum supply; not rated for 1.2 V operation like Nexperia's LVC version | Choose only if system VCC never drops below 1.65 V and TI sourcing is preferred |
Compared with 74LVCH16373ADL,118, the bus hold feature adds deterministic idle-state behavior without extra components; versus SN74ALVCH16373DGGR, the 74LVC16373ADL,118 supports deeper low-voltage operation critical for battery-backed subsystems.
Availability
74LVC16373ADL,118 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, test equipment digital pattern generation, and medical imaging data acquisition requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LVC16373ADL,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable logic, analog, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in demanding applications.
The 74LVC series targets low-voltage, high-speed digital interface applications where power efficiency, noise immunity, and mixed-voltage interoperability are critical design constraints.
FAQ
Is 74LVC16373ADL,118 pin-compatible with 74LVCH16373ADL,118?
Yes - both share identical TSSOP48 (SOT362-1) pinout, supply range, timing, and functional behavior. The sole difference is that 74LVCH16373ADL,118 includes bus hold on all data inputs, while 74LVC16373ADL,118 does not. No PCB redesign is needed for substitution, but bus hold functionality will be absent.
Can 74LVC16373ADL,118 operate at 1.2 V while interfacing with 5 V signals?
Yes - it is fully specified for 1.2 V to 3.6 V VCC operation and supports 5.5 V tolerant inputs/outputs. At 1.2 V supply, inputs accept 0–5.5 V logic levels, and outputs drive compatible loads within their 1.2 V VOH/VOL limits, enabling true level translation without external circuitry.
What is the purpose of the IOFF feature in this latch?
The IOFF circuit disables all outputs when VCC = 0 V, preventing reverse current flow from live 5 V buses into the unpowered device. This protects downstream circuitry during hot-swap, partial power-down, or battery-backup transitions - a requirement in automotive and industrial systems with multi-rail architectures.
Does 74LVC16373ADL,118 require external pull-up resistors on unused inputs?
No - unlike standard 74LVC variants, this specific part number (74LVC16373ADL,118) does not integrate bus hold. Only the 74LVCH16373A family includes bus hold. Therefore, unused data inputs on 74LVC16373ADL,118 must be externally terminated to VCC or GND to avoid floating states and potential shoot-through current.
74LVC16373ADL,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 48-BSSOP (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 8:8
- Output Type:
- Tri-State
- Voltage - Supply:
- 1.65V ~ 3.6V
- Independent Circuits:
- 2
- Delay Time - Propagation:
- 1ns
- Current - Output High, Low:
- 24mA, 24mA
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-SSOP
74LVC16373ADL,118 FAQ
1.How can I place an order for 74LVC16373ADL,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC16373ADL,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC16373ADL,118 reliable?
The price and inventory of 74LVC16373ADL,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC16373ADL,118 is usually 5 days.
3.What payment methods are accepted for 74LVC16373ADL,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC16373ADL,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC16373ADL,118?
74LVC16373ADL,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC16373ADL,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC16373ADL,118?
For technical support, including 74LVC16373ADL,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC16373ADL,118 requirements.
6.How does Aetrix verify that 74LVC16373ADL,118 is sourced from the original manufacturer or authorized distributors?
All 74LVC16373ADL,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC16373ADL,118 meets industry standards.
7.What is the process for return or replacement of 74LVC16373ADL,118?
All 74LVC16373ADL,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC16373ADL,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC16373ADL,118 part is unused and in its original packaging.
Return procedure for 74LVC16373ADL,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC16373ADL,118 Tags
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74AUP1G373GW,125
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NC7SZ373P6X
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