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Nexperia USA Inc. 74LVC373ABQ-Q100X

Part No.:
74LVC373ABQ-Q100X
Manufacturer:
Nexperia USA Inc.
Category:
Latches
Package:
20-VFQFN Exposed Pad
Datasheet:
Aetrix74LVC373ABQ-Q100X.pdf
Description:
IC D-TYPE TRANSP SGL 8:8 20HVQFN
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:4,022

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Product details

Overview

74LVC373ABQ-Q100 from Nexperia is an automotive-grade octal D-type transparent latch with 3-state outputs, latch enable (LE) and output enable (OE) controls, 1.2 V to 3.6 V supply operation, 5.5 V overvoltage-tolerant I/O, and Schmitt-trigger inputs for noise immunity. It functions as a data latching and bus isolation device in automotive body control modules requiring mixed-voltage interfacing between 3.3 V microcontrollers and 5 V sensors.

For engineers reviewing the 74LVC373ABQ-Q100 datasheet, 74LVC373ABQ-Q100 pinout, 74LVC373ABQ-Q100 application, or 74LVC373ABQ-Q100 equivalent, this device supports AEC-Q100 Grade 1 qualification (-40 °C to +125 °C), IOFF partial power-down protection, and DHVQFN20 side-wettable flank packaging for automated optical inspection in high-reliability automotive PCB assembly.

Technical Context

This latch operates in two primary modes: transparent mode when LE is HIGH (output Qn follows Dn in real time), and latched mode when LE transitions LOW (captures and holds Dn values at setup time). OE independently controls 3-state output impedance without affecting internal latch state.

Schmitt-trigger inputs tolerate slow rise/fall times and ensure robust switching across voltage domains; IOFF circuitry disables outputs and blocks backflow current when VCC = 0 V, enabling safe hot-insertion and partial power-down in multi-rail automotive systems.

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage 1.2 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families without level shifters.
I/O Voltage Tolerance Up to 5.5 V - allows connection to legacy 5 V peripherals while powered from 3.3 V rails, simplifying mixed-voltage board design.
Propagation Delay (D→Q) 1.5 ns to 8.5 ns (VCC = 3.0–3.6 V) - ensures sub-10 ns timing margin for high-speed data capture in CAN/LIN gateway interfaces.
IOFF Leakage Current ±10 μA max at VCC = 0 V - prevents damaging back-current during system power sequencing or module hot-swap events.
ESD Protection HBM > 2000 V, CDM > 1000 V - meets automotive ESD robustness requirements for under-hood and infotainment environments.
Operating Temperature -40 °C to +125 °C - qualified per AEC-Q100 Grade 1 for engine bay, transmission control, and ADAS sensor interface applications.
Output Drive Strength ±24 mA (VCC = 3.0 V) - sufficient to drive multiple CMOS/TTL loads or short PCB traces without external buffers.

Pinout & Package

DHVQFN20 package (SOT764-1), 2.5 × 4.5 × 0.85 mm body, side-wettable flanks for AOI-compatible solder joint inspection, no leads, thermal pad exposed on underside.

Pin/Terminal Circuit Role Design Meaning
1 OE (Output Enable) Active-LOW control: drives all eight outputs to high-impedance when HIGH; does not affect latch state.
2–9, 12–19 D0–D7 / Q0–Q7 Eight bidirectional data paths: Dn inputs feed latches; Qn outputs reflect latched or transparent data per LE state.
10 GND Ground reference (0 V); thermal pad beneath package must be connected to GND plane for thermal and EMI performance.
11 LE (Latch Enable) Active-HIGH control: HIGH enables transparency; LOW-to-HIGH transition captures Dn values at setup time.
20 VCC Core supply input (1.2–3.6 V); decoupling capacitor (100 nF) required within 5 mm of pin for stable switching.

Key Features

Feature Design Value
AEC-Q100 Grade 1 qualification Validated for automotive use from -40 °C to +125 °C ambient, including temperature cycling, humidity, and vibration stress testing.
5.5 V tolerant I/O with 1.2 V core Eliminates need for discrete level translators when interfacing 3.3 V MCUs with 5 V analog front-ends or legacy sensors.
IOFF partial power-down protection Automatically disables outputs and blocks reverse current when VCC is unpowered, preventing damage during power sequencing faults.
Schmitt-trigger inputs Provides hysteresis (typically 0.3–0.5 V) to reject noise on slow-rising signals from mechanical switches or long harness runs.
DHVQFN20 with side-wettable flanks Enables automated optical inspection of solder joints on bottom-side terminals, improving manufacturing yield in automotive SMT lines.

Applications

Body Control Module (BCM) Instrument Cluster Interface

Use Scenario: Latching status signals from door lock switches, window lift sensors, and lighting controls before multiplexing onto LIN/CAN bus.

IC Role / Device Role / Timing Role: Octal transparent latch synchronizes asynchronous mechanical inputs to MCU clock domain while providing 3-state isolation during bus arbitration.

Use Value: Enables deterministic sampling of noisy switch signals via Schmitt-trigger inputs and eliminates bus contention using OE-controlled high-impedance outputs.

Use Scenario: Buffering and isolating SPI or parallel display data between 3.3 V graphics controller and 5 V segment driver ICs in digital dashboards.

IC Role / Device Role / Timing Role: Data latch holds pixel or command data stable during display refresh cycles; 3-state outputs prevent signal corruption during controller reconfiguration.

Use Value: 5.5 V I/O tolerance permits direct connection to 5 V display drivers without level-shifting components, reducing BOM count and layout area.

Power Distribution Unit (PDU) ADAS Camera Interface

Use Scenario: Isolating diagnostic communication lines (e.g., UDS over CAN) from high-noise power switching circuits in 12 V/48 V hybrid vehicle PDUs.

IC Role / Device Role / Timing Role: Latch enables controlled gating of diagnostic data paths; IOFF protection prevents backfeed into unpowered diagnostic ports during maintenance.

Use Value: IOFF functionality ensures safe hot-plug capability for service tools, while 125 °C rating supports under-hood deployment near DC-DC converters.

Use Scenario: Capturing parallel image data from CMOS image sensors before serialization for MIPI CSI-2 transmission in surround-view camera modules.

IC Role / Device Role / Timing Role: Transparent latch aligns sensor pixel data to system clock edge; low propagation delay (<8.5 ns) preserves timing margins for high-resolution streaming.

Use Value: Sub-10 ns D→Q delay and ±24 mA drive strength support reliable capture of 24-bit RGB parallel video at up to 25 MHz pixel clocks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Alternative Part Technical Difference Application Difference Selection Advice
74LVC373APW-Q100 TSSOP20 package (SOT360-1), 4.4 mm body width, no side-wettable flanks Lacks AOI-compatible solder joint inspection; suitable for non-automotive or lower-volume production where optical verification is not mandated Select when footprint compatibility with legacy TSSOP layouts is required and AOI is not enforced by manufacturing process.
SN74LVC373AQPWRQ1 Texas Instruments variant; identical function but different IOFF leakage spec (±20 μA vs. ±10 μA) and JEDEC-compliance scope Approved for automotive use but lacks Nexperia's DHVQFN20 thermal enhancement and side-wettable flank geometry Choose only if TI supply chain alignment or existing TI-based BOM consolidation outweighs Nexperia's thermal and manufacturability advantages.

Compared with 74LVC373APW-Q100, the BQ variant offers superior thermal dissipation and automated optical inspection capability; versus SN74LVC373AQPWRQ1, it delivers tighter IOFF leakage control and optimized package geometry for high-reliability automotive SMT processes.

Availability

74LVC373ABQ-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, instrument cluster interfaces, power distribution units, and ADAS camera subsystems requiring stable component supply with AEC-Q100 compliance and extended temperature operation.

Supply support for 74LVC373ABQ-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, with leadership in automotive-qualified components and advanced packaging technologies.

The 74LVC373A-Q100 belongs to Nexperia's automotive logic family, designed specifically for robust data latching and bus isolation in harsh-temperature, mixed-voltage automotive ECUs where safety, longevity, and manufacturability are critical.

FAQ

What is the maximum input voltage the 74LVC373ABQ-Q100 can tolerate on its I/O pins?

The device supports up to 5.5 V on all input and output pins regardless of VCC level, enabling safe interfacing with 5 V peripherals while operating from a 1.2 V to 3.6 V supply. This overvoltage tolerance is guaranteed across the full -40 °C to +125 °C temperature range and does not require external clamping diodes.

How does the IOFF feature protect the device during partial power-down?

When VCC = 0 V, the IOFF circuitry automatically disables all outputs and blocks current flow between powered and unpowered sections of the system. Measured IOFF leakage is ≤±10 μA at 5.5 V applied to I/O pins, preventing back-current damage during power sequencing, sleep mode transitions, or hot-swap events in automotive modules.

Can the 74LVC373ABQ-Q100 operate reliably at 1.2 V supply voltage?

Yes - the device is fully specified down to 1.2 V VCC, with guaranteed propagation delay (≤14 ns), output drive (≥±4 mA), and input thresholds (VIH ≥ 1.08 V, VIL ≤ 0.12 V) at that voltage. All static and dynamic parameters in Tables 6 and 7 include 1.2 V test conditions, confirming functional operation in ultra-low-power automotive subsystems.

Is the DHVQFN20 package compatible with standard reflow profiles for lead-free soldering?

Yes - the SOT764-1 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 3 and supports standard lead-free reflow profiles (peak 260 °C, 60 s above 217 °C). Its side-wettable flanks are designed for compatibility with automated optical inspection systems used in Tier-1 automotive manufacturing lines.

74LVC373ABQ-Q100X Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74LVC
Package/Case:
20-VFQFN Exposed Pad
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
D-Type Transparent Latch
Circuit:
8:8
Output Type:
Tri-State
Voltage - Supply:
1.2V ~ 3.6V
Independent Circuits:
1
Delay Time - Propagation:
3.3ns
Current - Output High, Low:
24mA, 24mA
Operating Temperature:
-40°C ~ 125°C
Grade:
Automotive
Qualification:
AEC-Q100
Mounting Type:
Surface Mount
Supplier Device Package:
20-DHVQFN (4.5x2.5)

74LVC373ABQ-Q100X FAQ

1.How can I place an order for 74LVC373ABQ-Q100X through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LVC373ABQ-Q100X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LVC373ABQ-Q100X reliable?

The price and inventory of 74LVC373ABQ-Q100X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC373ABQ-Q100X is usually 5 days.

3.What payment methods are accepted for 74LVC373ABQ-Q100X?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC373ABQ-Q100X transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LVC373ABQ-Q100X?

74LVC373ABQ-Q100X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LVC373ABQ-Q100X order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LVC373ABQ-Q100X?

For technical support, including 74LVC373ABQ-Q100X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC373ABQ-Q100X requirements.

6.How does Aetrix verify that 74LVC373ABQ-Q100X is sourced from the original manufacturer or authorized distributors?

All 74LVC373ABQ-Q100X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC373ABQ-Q100X meets industry standards.

7.What is the process for return or replacement of 74LVC373ABQ-Q100X?

All 74LVC373ABQ-Q100X units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC373ABQ-Q100X, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LVC373ABQ-Q100X part is unused and in its original packaging.

Return procedure for 74LVC373ABQ-Q100X:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

74LVC373ABQ-Q100X Tags

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