NXP Semiconductors 74LVC373AD,112

Overview

74LVC373AD,112 from Nexperia is an octal D-type transparent latch with 3-state outputs, latch enable (LE) and output enable (OE) control, 5 V tolerant I/O, and operation across 1.2 V to 3.6 V supply. It functions as a bidirectional data latching interface in mixed-voltage digital systems, supporting transparent mode (LE HIGH), latch mode (LE LOW), and high-impedance output disable (OE HIGH). Used in bus buffering, address/data latching, and level translation between 3.3 V and 5 V subsystems.

For engineers reviewing the 74LVC373AD,112 datasheet, 74LVC373AD,112 pinout, 74LVC373AD,112 application, or 74LVC373AD,112 equivalent, this device is selected for precise timing-critical latching in industrial controllers, FPGA I/O expansion, and legacy bus interfacing where voltage translation, low static power, and IOFF-enabled partial power-down are required.

Technical Context

The 74LVC373AD implements eight independent D-type latches with Schmitt-trigger inputs for noise immunity and robust edge handling. Its dual-control architecture separates data capture (via LE) from output driver enable (via OE), enabling independent timing management of latching and bus release.

IOFF circuitry actively disables outputs when VCC = 0 V, blocking backflow current during hot-swap or partial power-down sequences. Input tolerance up to 5.5 V allows direct connection to 5 V logic without external level shifters, while CMOS design ensures sub-μA ICC at standby and fast propagation delays down to 1.5 ns at 3.3 V.

Key Specifications

Pinout & Package

74LVC373AD,112 is supplied in SO20 (SOT163-1) plastic small outline package: 20-pin, 7.5 mm body width, 1.27 mm pitch, gull-wing leads. Pin 1 index located at top-left corner with notch marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with SN74LVC373APWR and 74LVCH373APWJ, the 74LVC373AD,112 provides superior thermal performance in SO20, guaranteed 5 V tolerance for legacy interoperability, and lower input leakage-making it optimal for industrial and automotive bus bridging where reliability and voltage flexibility are mandatory.

Availability

74LVC373AD,112 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, FPGA configuration latching, and legacy bus interface bridge applications requiring stable component supply across extended temperature and mixed-voltage operating conditions.

Supply support for 74LVC373AD,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, analog, and MOSFET solutions with focus on efficiency, miniaturization, and robustness for industrial and automotive markets.

The 74LVC373A series belongs to Nexperia's advanced LVC logic family, designed specifically for low-voltage, high-noise-immunity digital interfacing in harsh environments where voltage translation, partial power-down, and wide temperature operation are essential.

FAQ

Can 74LVC373AD,112 operate with VCC = 1.2 V while accepting 5 V inputs?

Yes. The device is fully specified from 1.2 V to 3.6 V supply and supports input voltages up to 5.5 V independent of VCC. At 1.2 V VCC, VIH is 1.08 V min and VIL is 0.12 V max, and input clamping current remains within ±50 mA limits per Absolute Maximum Ratings Table 4. This enables true 5 V-to-1.2 V translation without external components.

What is the maximum output current per pin when VCC = 3.3 V?

At VCC = 3.3 V, the device guarantees VOH ≥ 2.2 V at −24 mA (source) and VOL ≤ 0.55 V at 24 mA (sink), per Static Characteristics Table 6. These are absolute maximum ratings under recommended operating conditions; continuous operation at 24 mA per pin requires thermal derating per Ptot limits in Table 4 (500 mW for SO20, derating 12.3 mW/K above 109 °C).

How does the IOFF feature behave during power sequencing?

When VCC drops to 0 V, the IOFF circuitry forces all outputs into high-impedance state regardless of OE or LE logic levels. Measured IOFF leakage is ±10 μA max at VI or VO = 5.5 V, preventing back-current flow into powered-down sections. This behavior is guaranteed across −40 °C to +125 °C and eliminates need for external isolation FETs in hot-swap architectures.

Is the 74LVC373AD,112 pin-compatible with older 74HC373 devices?

No. While both are octal transparent latches with OE/LE controls, 74LVC373AD uses different voltage thresholds (VIH = 0.65×VCC vs. 0.7×VCC for HC), lower propagation delay (1.5–6.8 ns vs. 15–25 ns), and 5 V tolerant I/O (HC is not). Pinout matches standard 20-pin SO, but electrical behavior differs significantly-direct replacement requires validation of timing margins and voltage compatibility.