Nexperia USA Inc. 74LVC373AD,118

Overview

74LVC373AD,118 from Nexperia is an octal D-type transparent latch with 3-state outputs, latch enable (LE) and output enable (OE) controls, 1.2 V to 3.6 V supply operation, 5 V tolerant I/O, and Schmitt-trigger inputs for noise immunity. It functions as a data latching and bus isolation interface in mixed-voltage digital systems such as industrial control backplanes and FPGA I/O expansion.

For engineers reviewing the 74LVC373AD,118 datasheet, 74LVC373AD,118 pinout, 74LVC373AD,118 application, or 74LVC373AD,118 equivalent, key selection criteria include 3-state timing (t_en/t_dis ≤ 10 ns), IOFF-enabled partial power-down capability, ±50 mA output drive, and SO20 package compatibility with legacy 74-series footprint layouts.

Technical Context

The device implements eight independent D-latches with synchronous transparent mode (LE HIGH) and edge-triggered capture (LE HIGH-to-LOW transition). Latch state retention is maintained during OE assertion, enabling independent output gating without affecting stored data.

Schmitt-trigger inputs ensure robust operation with slow-rising signals (Δt/ΔV up to 20 ns/V at V_CC = 1.65 V), while the IOFF circuit disables outputs when V_CC = 0 V, preventing backflow current in hot-swap or power-gated subsystems.

Key Specifications

Pinout & Package

74LVC373AD,118 is supplied in SO20 (SOT163-1) plastic small outline package: 20-pin, 7.5 mm body width, 1.27 mm pitch, gull-wing leads, JEDEC MS-013 compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with SN74LVC373APWR and 74LVC373APW,118, the 74LVC373AD,118 offers drop-in replacement in SO20 footprints, lower thermal resistance in free-air environments, and direct compatibility with existing 74-series socket adapters used in validation labs.

Availability

74LVC373AD,118 is available at Aetrix Electronics and suitable for industrial automation interfaces, FPGA peripheral expansion, automotive body control modules, and automated test equipment requiring stable component supply across extended temperature ranges.

Supply support for 74LVC373AD,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVC373A series targets mixed-voltage digital interfacing, emphasizing robustness in partial-power-down scenarios, wide supply range flexibility, and seamless integration into legacy 74-series designs.

FAQ

What is the maximum clock frequency supported by the 74LVC373AD,118?

The 74LVC373AD,118 does not operate on a clock signal-it is a transparent latch controlled by the LE input. Its usable data rate is determined by propagation delay (as low as 1.5 ns) and setup/hold times (2.0 ns/1.5 ns at V_CC = 3.3 V), enabling reliable operation with bus cycles down to ~100 MHz in latch-enable-gated systems.

Can the 74LVC373AD,118 be used with a 5 V microcontroller driving its inputs?

Yes-its inputs are rated for 0 V to 5.5 V regardless of V_CC, allowing direct connection to 5 V TTL or CMOS outputs. When V_CC = 3.3 V, outputs swing rail-to-rail (0 V to 3.3 V) and remain compatible with 5 V-tolerant receivers due to the 5 V I/O rating.

Does the 74LVC373AD,118 support hot-swap insertion when V_CC is unpowered?

Yes-the IOFF circuit actively disables outputs when V_CC = 0 V, limiting OFF-state leakage to ±10 μA maximum. This prevents back-current flow from live 5 V buses into the unpowered IC, satisfying IEC 61000-4-2 hot-swap safety requirements.

How does the Schmitt-trigger input improve noise immunity compared to standard CMOS inputs?

Schmitt-trigger inputs provide hysteresis (typically 0.3 V to 0.5 V depending on V_CC), meaning the threshold for rising edges (~0.7 × V_CC) differs from falling edges (~0.3 × V_CC). This eliminates chatter on slow or noisy signals-such as those from long cables or mechanical switches-and prevents false triggering during signal transitions.