Nexperia USA Inc. 74LVC373ADB,112

Overview

74LVC373ADB,112 from Nexperia is an octal D-type transparent latch with 3-state outputs, latch enable (LE) and output enable (OE) controls, 1.2 V to 3.6 V supply operation, 5 V tolerant I/O, and Schmitt-trigger inputs for noise immunity. It functions as a data latching and bus isolation interface in mixed-voltage digital systems such as industrial control backplanes and microcontroller peripheral expansion.

For engineers reviewing the 74LVC373ADB,112 datasheet, 74LVC373ADB,112 pinout, 74LVC373ADB,112 application, or 74LVC373ADB,112 equivalent, this device supports voltage translation between 3.3 V logic domains and legacy 5 V peripherals while enabling precise timing-controlled data capture and high-impedance bus sharing in embedded system interconnects.

Technical Context

The 74LVC373ADB,112 implements eight independent D-type latches with transparent mode when LE is HIGH and edge-triggered storage on LE HIGH-to-LOW transition. Its IOFF circuitry ensures zero backflow current during partial power-down, meeting JEDEC JESD8-7A/5A/C standards across 1.65–3.6 V operation.

Schmitt-trigger inputs tolerate slow-rising signals up to 20 ns/V at 1.65 V and 10 ns/V at 3.6 V, while propagation delays range from 1.5 ns (min) to 9.0 ns (max) at VCC = 3.0–3.6 V. Output skew is guaranteed ≤1.5 ns per latch, supporting synchronized multi-bit data retention.

Key Specifications

Pinout & Package

74LVC373ADB,112 uses the SOT339-1 (SSOP20) package: plastic shrink small outline, 20 leads, body width 5.3 mm, pitch 0.65 mm, lead count 20, thermal resistance θJA ≈ 120 K/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with SN74LVC373APWR, the 74LVC373ADB,112 offers better mechanical compatibility with legacy SSOP footprints and slightly lower assembly cost, while 74LVCH373APW,118 adds bus-hold functionality at the expense of marginally higher ICC in high-impedance states.

Availability

74LVC373ADB,112 is available at Aetrix Electronics and suitable for industrial PLC backplane interfaces, microcontroller GPIO expansion, and automotive body control modules requiring stable component supply across extended temperature ranges and mixed-voltage operation.

Supply support for 74LVC373ADB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer applications.

The 74LVC373A series belongs to Nexperia's advanced LVC logic family, designed specifically for low-voltage, mixed-signal interfacing with robust voltage translation, partial power-down capability, and wide ambient temperature operation.

FAQ

What is the maximum clock/data rate supported by the 74LVC373ADB,112?

The 74LVC373ADB,112 does not operate on a clock signal but responds to LE and OE control edges. Its minimum propagation delay is 1.5 ns (tpd) and maximum is 9.0 ns at VCC = 3.0–3.6 V, enabling reliable data capture at effective rates exceeding 100 MHz in transparent mode when LE is held HIGH and input transitions meet specified slew-rate limits (≤10 ns/V).

Can the 74LVC373ADB,112 safely interface a 3.3 V microcontroller with a 5 V LCD display?

Yes. The 74LVC373ADB,112 accepts 0–5.5 V inputs and delivers 0–VCC outputs, so with VCC = 3.3 V it safely buffers 3.3 V MCU signals to 5 V-tolerant LCD control lines. Its 5 V tolerant outputs drive the LCD directly without level shifters, provided the LCD's input leakage remains within ±20 μA (per datasheet IOZ spec).

Does the 74LVC373ADB,112 support hot-swap or live-insertion into a powered system?

Yes, via its IOFF circuitry. When VCC = 0 V, the IOFF feature disables outputs and limits backflow current to ±10 μA maximum, preventing damage during insertion into a live 5 V bus. This is explicitly verified per JEDEC JESD78 and documented in Section 7 (Limiting Values) of the datasheet.

How does the Schmitt-trigger input improve noise immunity compared to standard CMOS inputs?

Schmitt-trigger inputs provide hysteresis (~0.3 V at VCC = 3.3 V), meaning VIH and VIL thresholds differ by that amount. This prevents multiple output toggles when input signals cross the threshold slowly or with noise, making the device robust against EMI on long PCB traces or unshielded cables-critical in industrial control and test equipment environments.