NXP Semiconductors 74LVC373ADB,118

Overview

74LVC373ADB,118 from Nexperia is an octal D-type transparent latch with 3-state outputs, latch enable (LE) and output enable (OE) control, 5 V tolerant I/O, 1.2 V to 3.6 V supply range, and Schmitt-trigger inputs for noise immunity in mixed-voltage digital systems-used in bus interface buffering and data latching in industrial microcontroller peripherals.

For engineers reviewing the 74LVC373ADB,118 datasheet, 74LVC373ADB,118 pinout, 74LVC373ADB,118 application, or 74LVC373ADB,118 equivalent, this page delivers verified functional behavior, JEDEC-compliant voltage translation capability, IOFF partial power-down support, and SO20 package-specific timing and thermal derating data required for robust PCB layout and system-level timing closure.

Technical Context

The device implements eight independent D-type latches with transparent mode when LE is HIGH and edge-triggered capture on LE HIGH-to-LOW transition. Each latch output drives a 3-state buffer controlled separately by OE (active LOW), enabling shared-bus applications without affecting internal latch state.

Inputs tolerate up to 5.5 V regardless of VCC (1.2–3.6 V), supporting bidirectional level translation between 3.3 V logic and legacy 5 V subsystems. The IOFF circuit ensures zero backflow current during partial power-down, and Schmitt-trigger inputs accept slow-rising signals down to 10 ns/V slew rate at 3.6 V.

Key Specifications

Pinout & Package

74LVC373ADB,118 is packaged in SO20 (SOT163-1): plastic small outline, 20-pin, 7.5 mm body width, 1.27 mm pitch, surface-mountable with gull-wing leads.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with SN74LVC373APWR and 74LVC373APW,118, the 74LVC373ADB,118 offers superior mechanical robustness in vibration-prone environments due to SO20's longer gull-wing leads and higher IPC Class 3 solder joint reliability, while maintaining identical logic functionality and voltage translation capability.

Availability

74LVC373ADB,118 is available at Aetrix Electronics and suitable for industrial automation controllers, automotive body electronics, test equipment signal generation, and medical imaging subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LVC373ADB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74LVC373A series belongs to Nexperia's advanced logic portfolio designed specifically for voltage translation, bus isolation, and data latching in energy-efficient industrial and automotive electronics where mixed-supply interoperability and partial power-down are mandatory.

FAQ

What is the maximum input voltage the 74LVC373ADB,118 can safely accept on its D and control pins?

The device accepts up to 5.5 V on all inputs-including D0–D7, LE, and OE-regardless of VCC setting (1.2 V to 3.6 V). This is explicitly guaranteed in Table 4 (Limiting Values) and Table 5 (Recommended Operating Conditions) of the datasheet, enabling direct interfacing with 5 V TTL sources without external clamping or level-shifting circuitry.

Does the 74LVC373ADB,118 support hot insertion or partial power-down operation?

Yes-the IOFF circuitry actively disables outputs and limits leakage to ±10 μA when VCC = 0 V, preventing damaging back-current flow through powered-down sections of a system. This feature is fully characterized per JEDEC JESD78 and validated across −40 °C to +125 °C, making it suitable for hot-swap backplane and modular power architecture designs.

How does the Schmitt-trigger input improve noise immunity in real-world applications?

Schmitt-trigger action provides ≥0.5 V hysteresis on all inputs, meaning a rising signal must exceed VIH by at least that margin before registering HIGH, and a falling signal must drop below VIL by the same amount before registering LOW. This rejects high-frequency noise spikes and slow-rising edges common in long PCB traces or unshielded harnesses, eliminating false triggering in factory-floor or vehicle environments.

What is the minimum pulse width required on the LE input to reliably capture data?

The minimum LE HIGH pulse width is 3.0 ns at VCC = 3.0–3.6 V (Table 7, tW parameter), verified across −40 °C to +125 °C. This allows reliable latching from fast FPGA or microcontroller GPIO toggling without external timing constraints, provided setup (2.0 ns) and hold (1.5 ns) times are also met relative to the LE edge.