Diodes Incorporated 74LVC373AQ20-13

Overview

74LVC373AQ20-13 from Diodes Incorporated is an octal transparent D-type latch with 3-state outputs in a 20-pin V-QFN4525 package (2.5 mm × 4.5 mm, 0.5 mm pitch), operating from 1.65 V to 3.6 V supply, supporting 5.5 V-tolerant inputs and ±24 mA output drive at 3.0 V - used for bidirectional bus interfacing in low-voltage embedded control systems.

For engineers reviewing the 74LVC373AQ20-13 datasheet, 74LVC373AQ20-13 pinout, 74LVC373AQ20-13 application, or 74LVC373AQ20-13 equivalent, key selection criteria include latch-enable timing (tSU = 2.0 ns min @ 3.3 V), 3-state enable/disable speed (tEN/tDIS = 7.5 ns typ @ 3.3 V), IOFF-enabled partial power-down capability, and mixed-voltage signal translation between 3.3 V and 5 V domains.

Technical Context

This device implements eight independent edge-transparent latches with asynchronous 3-state control: latch operation is enabled when LE is high (Q follows D); data is captured on LE falling edge; OE independently places all outputs in high-impedance without affecting internal latch state. The IOFF circuit disables outputs during power-down to prevent backflow current.

All inputs feature Schmitt-trigger action for noise immunity, and the design supports simultaneous retention of latched data and new input acceptance while outputs are disabled - enabling glitch-free bus arbitration and hot-swap-ready signal isolation in multi-supply systems.

Key Specifications

Pinout & Package

V-QFN4525-20 package: 2.5 mm × 4.5 mm body, 0.5 mm lead pitch, exposed thermal pad (pin 20 is VCC, pin 10 is GND, no dedicated thermal pad pin - pad connected internally to GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal transparent latch applications.

Compared with SN74LVC373APWR, the 74LVC373AQ20-13 offers 29% smaller footprint and 9% lower thermal resistance; versus 74LVCH16373ADGG, it provides half the channel count but enables tighter routing and lower BOM cost in 8-bit-only systems.

Availability

74LVC373AQ20-13 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, embedded microcontroller bus interface, and low-power data acquisition modules requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for 74LVC373AQ20-13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and logic solutions, with emphasis on high-reliability, energy-efficient components for industrial and computing markets.

The 74LVC373A belongs to Diodes' LVC logic family - designed specifically for low-voltage, mixed-signal interfacing where robustness, voltage tolerance, and partial power-down capability are essential in space-constrained embedded systems.

FAQ

Can 74LVC373AQ20-13 operate with VCC = 1.5 V?

No. The absolute minimum recommended VCC is 1.65 V per DS35893 Rev. 1–2 Section 6. Operating below this violates the Recommended Operating Conditions and may cause unpredictable latch behavior, increased propagation delay variation, or failure to retain state under temperature extremes. Data retention is specified only down to 1.5 V, not functional operation.

What is the maximum capacitive load the outputs can drive reliably?

The datasheet specifies timing parameters up to 30 pF load capacitance (Figure 1 test condition). Driving >50 pF may exceed tPD and tEN specifications, especially at 3.3 V, due to increased RC time constant. For >30 pF loads, reduce VCC to 2.7 V or add series termination resistors to limit slew rate and maintain signal integrity.

Is the exposed thermal pad on the QFN package electrically connected?

Yes - the exposed pad is internally connected to GND per Diodes' AP02002 package drawing and recommended layout AP02001. It must be soldered to a solid GND plane with ≥4 thermal vias (0.3 mm diameter) to achieve the published θJA = 67°C/W. Leaving it floating degrades thermal performance by >40% and risks latch-up under transient stress.

Does OE affect internal latch state when asserted?

No. As stated in the Description section, "OE does not affect the internal operations of the latches." The Q outputs enter high-impedance regardless of LE or D input states, but stored data remains intact and fully recoverable upon OE deassertion - enabling concurrent data update (via D inputs) and bus release without loss of latched values.