Nexperia USA Inc. 74LVC573ABQ,115
- Part No.:
- 74LVC573ABQ,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Latches
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
74LVC573ABQ,115.pdf
- Description:
- IC D-TYPE TRANSP SGL 8:8 20HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:13,354
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Product details
Overview
74LVC573ABQ,115 from Nexperia is an octal D-type transparent latch with 3-state outputs, latch enable (LE) and output enable (OE) control, 1.2 V to 3.6 V supply operation, 5.5 V overvoltage-tolerant inputs/outputs, and Schmitt-trigger inputs for noise immunity-used in bus interface and level translation between 3.3 V and 5 V subsystems in industrial I/O controllers.
For engineers reviewing the 74LVC573ABQ,115 datasheet, 74LVC573ABQ,115 pinout, 74LVC573ABQ,115 application, or 74LVC573ABQ,115 equivalent, this device supports partial power-down (IOFF), operates from –40 °C to +125 °C, delivers sub-8 ns propagation delay at 3.3 V, and enables bidirectional voltage translation without external biasing.
Technical Context
The 74LVC573ABQ implements eight independent D-latches with synchronous transparent mode (LE HIGH) and edge-triggered latching (LE HIGH-to-LOW transition), where data is captured one setup time before LE falls. Its dual enable architecture isolates latch state (LE) from output drive (OE), allowing stored data retention while outputs float.
Schmitt-trigger inputs ensure robust timing with slow-rising signals, and the IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current during hot-swap or partial power-down sequences-critical for mixed-voltage backplane and modular PLC designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage (VCC) | 1.2 V to 3.6 V - supports single-supply operation across low-voltage logic families including 1.8 V and 2.5 V systems. |
| Input voltage tolerance | –0.5 V to 5.5 V - enables direct interfacing with 5 V TTL or CMOS drivers without level-shifting components. |
| Propagation delay (Dn→Qn) | 1.5 ns (min) to 6.2 ns (max) at VCC = 3.0–3.6 V - ensures tight timing alignment in high-speed address/data latching. |
| IOFF leakage current | ±10 μA max at VCC = 0 V, VI/VO = 5.5 V - guarantees safe hot-insertion and prevents backfeed into powered-down rails. |
| Operating temperature | –40 °C to +125 °C - qualified for under-hood automotive modules, industrial motor drives, and outdoor telecom equipment. |
| ESD protection | HBM >2000 V, CDM >1000 V - meets IEC 61000-4-2 system-level robustness requirements for field-deployable hardware. |
| Power dissipation capacitance | 13.2 pF - enables accurate dynamic power estimation (PD = CPD × VCC² × fi × N) for thermal budgeting in dense PCB layouts. |
Pinout & Package
DHVQFN20 package (SOT764-1): 2.5 mm × 4.5 mm × 0.85 mm body, 20-terminal quad flat no-lead with exposed thermal pad (non-soldered or floating GND connection per datasheet).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE (output enable) | Active-low control: drives all Q0–Q7 into high-impedance state independently of latch content; no effect on internal storage. |
| 2–9 | D0–D7 (data inputs) | Asynchronous input terminals accepting 5.5 V tolerant signals; Schmitt-triggered for noise margin up to 0.8 V hysteresis. |
| 10 | GND | Ground reference; thermal pad (terminal 1 index area) may be left floating or connected to GND per layout requirements. |
| 11 | LE (latch enable) | Active-high transparent control: HIGH enables real-time D→Q pass-through; LOW captures and holds data on falling edge. |
| 12–19 | Q0–Q7 (latched outputs) | 3-state buffered outputs with rail-to-rail swing (VOL ≤ 0.55 V @ 24 mA sink); support bus sharing and fanout to 10 LVC loads. |
| 20 | VCC | Primary supply rail (1.2–3.6 V); powers internal logic and output buffers; IOFF active only when VCC = 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| 5.5 V overvoltage-tolerant I/O | Allows direct connection to legacy 5 V microcontrollers or FPGAs without external translators-reducing BOM count and board space. |
| IOFF partial power-down | Prevents destructive back-current flow when VCC is unpowered, enabling safe insertion/removal in live backplanes or modular I/O racks. |
| Schmitt-trigger inputs | Provides ≥0.4 V hysteresis at 3.3 V supply, eliminating need for external RC filters on noisy industrial sensor or switch inputs. |
| Flow-through pinout | Input (D0–D7) and output (Q0–Q7) pins are arranged in mirrored order (pins 2–9 and 12–19), simplifying PCB routing and reducing trace crosstalk. |
| JEDEC-compliant voltage ranges | Validated across JESD8-7A (1.65–1.95 V), JESD8-5A (2.3–2.7 V), and JESD8-C/JESD36 (2.7–3.6 V)-ensures interoperability with multi-rail SoCs. |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating microcontroller GPIOs from high-current solenoid drivers and relay banks in modular I/O cards. IC Role / Device Role / Timing Role: Acts as a bidirectional bus latch-capturing command data from MCU during LE pulse, then driving outputs while OE enables driver ICs. Use Value: Enables 5 V actuator compatibility with 3.3 V MCU logic, eliminates level shifter ICs, and provides glitch-free output hold during MCU reset sequences. |
Use Scenario: Interfacing infotainment head-unit processors with 5 V CAN transceivers and LIN slave nodes in centralized gateway ECUs. IC Role / Device Role / Timing Role: Buffers and translates UART/SPI control lines between 1.8 V application processor and 5 V physical layer ICs during power sequencing. Use Value: Maintains signal integrity across voltage domains without timing skew; IOFF prevents backfeed during sleep-mode transitions (e.g., key-off battery drain mitigation). |
| Test Equipment Digital Pattern Generator | Medical Diagnostic Imaging Interface |
|
Use Scenario: Generating synchronized digital stimulus waveforms for ASIC validation using FPGA-controlled parallel buses. IC Role / Device Role / Timing Role: Latches pattern data from FPGA fabric and presents stable outputs to DUT under precise LE timing control. Use Value: Sub-8 ns propagation delay and <1.5 ns output skew guarantee deterministic timing margins for high-speed boundary-scan testing. |
Use Scenario: Isolating radiation-hardened FPGA configuration buses from analog front-end ADC/DAC modules in portable ultrasound systems. IC Role / Device Role / Timing Role: Provides galvanic separation between digital control domain and sensitive analog signal paths via 3-state output disable. Use Value: Prevents digital switching noise coupling into analog acquisition chains; Schmitt inputs reject EMI from nearby RF transceivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal transparent latch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC573APWRE4 | TSSOP20 package (SOT360-1); identical electrical specs but 4.4 mm body width and 0.65 mm pitch-less thermal mass than DHVQFN. | Better suited for manual rework or low-volume prototyping due to larger pad spacing; lower thermal performance in continuous 24 mA drive scenarios. | Select for lab validation or small-batch builds where soldering yield and test probe access outweigh thermal density needs. |
| 74LVCH573AQ20,115 | Includes bus-hold circuitry on all inputs (no external pull-ups required); otherwise identical pinout, timing, and voltage specs. | Reduces external passive count in floating-bus applications (e.g., shared memory address latches), but increases input capacitance by ~1.5 pF. | Choose when managing unterminated stubs or intermittent connections-especially in ruggedized field instruments with long cable runs. |
Compared with SN74LVC573APWRE4, the 74LVC573ABQ,115 offers superior thermal dissipation (12.9 mW/K derating vs. 10.0 mW/K) and smaller footprint; versus 74LVCH573AQ20,115, it avoids bus-hold-induced input loading-critical for high-frequency clock distribution paths.
Availability
74LVC573ABQ,115 is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, medical diagnostics, and test equipment requiring stable component supply across extended temperature and mixed-voltage environments.
Supply support for 74LVC573ABQ,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies-including logic, discrete, and MOSFET solutions-designed for high-volume, high-reliability applications.
The 74LVC573A series belongs to Nexperia's advanced LVC logic family, engineered specifically for low-voltage, mixed-signal interfacing in space-constrained industrial and automotive control systems.
FAQ
Can the 74LVC573ABQ,115 operate with a 1.2 V supply and still tolerate 5 V inputs?
Yes. The device is fully specified at VCC = 1.2 V and maintains 5.5 V overvoltage tolerance on all inputs per datasheet Table 5 and Table 4. Input clamping diodes and oxide-thickness design prevent damage or leakage exceeding ±50 mA, even when VCC is at minimum rating.
What is the maximum output drive strength at 3.3 V supply?
At VCC = 3.3 V, the 74LVC573ABQ,115 sinks 24 mA with VOL ≤ 0.55 V and sources 24 mA with VOH ≥ 2.2 V (Table 6). This supports direct driving of standard LVC/LVT logic loads or LED indicators with series resistors down to 100 Ω.
Does the DHVQFN20 package require soldering the thermal pad?
No. Per datasheet Section 5.1, the exposed pad (terminal 1 index area) has no electrical or mechanical requirement to be soldered. If connected, it must remain electrically floating or tied to GND-never to VCC or signal nets-to avoid compromising IOFF functionality or thermal performance.
How does the IOFF feature behave during brown-out conditions?
IOFF activates only when VCC reaches 0 V-not during brown-out. During undervoltage (e.g., VCC = 0.8 V), outputs remain functional but timing and logic thresholds degrade per Table 6. True IOFF protection requires full power removal, making it effective for hot-swap, not brown-out recovery.
74LVC573ABQ,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 8:8
- Output Type:
- Tri-State
- Voltage - Supply:
- 1.2V ~ 3.6V
- Independent Circuits:
- 1
- Delay Time - Propagation:
- 1.5ns
- Current - Output High, Low:
- 24mA, 24mA
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-DHVQFN (4.5x2.5)
74LVC573ABQ,115 FAQ
1.How can I place an order for 74LVC573ABQ,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC573ABQ,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC573ABQ,115 reliable?
The price and inventory of 74LVC573ABQ,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC573ABQ,115 is usually 5 days.
3.What payment methods are accepted for 74LVC573ABQ,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC573ABQ,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC573ABQ,115?
74LVC573ABQ,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC573ABQ,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC573ABQ,115?
For technical support, including 74LVC573ABQ,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC573ABQ,115 requirements.
6.How does Aetrix verify that 74LVC573ABQ,115 is sourced from the original manufacturer or authorized distributors?
All 74LVC573ABQ,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC573ABQ,115 meets industry standards.
7.What is the process for return or replacement of 74LVC573ABQ,115?
All 74LVC573ABQ,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC573ABQ,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC573ABQ,115 part is unused and in its original packaging.
Return procedure for 74LVC573ABQ,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC573ABQ,115 Tags

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