Nexperia USA Inc. 74LVCH162373ADGG:1

Overview

74LVCH162373ADGG:1 from Nexperia is a 16-bit D-type transparent latch with integrated 30 Ω series termination resistors, 5 V tolerant I/O, and dual 8-bit 3-state outputs controlled by independent latch enable (1LE/2LE) and output enable (1OE/2OE) inputs. It operates from 1.2 V to 3.6 V, supports mixed-voltage translation between 3.3 V and 5 V systems, and features bus hold on all data inputs for floating-input immunity. It is used in high-speed address/data latching for industrial microcontroller buses and FPGA I/O expansion.

For engineers reviewing the 74LVCH162373ADGG:1 datasheet, 74LVCH162373ADGG:1 pinout, 74LVCH162373ADGG:1 application, or 74LVCH162373ADGG:1 equivalent, this device delivers deterministic transparent/latched timing, IOFF-enabled partial power-down protection, Schmitt-trigger input noise immunity, and TSSOP48 packaging optimized for dense PCB layouts in embedded control and communications interfaces.

Technical Context

This latch implements two independent 8-bit sections, each with separate D-inputs, latch enables, and output enables-enabling flexible partitioning as either two 8-bit or one unified 16-bit latch. Its bus hold circuitry actively maintains logic states on unused data inputs without external pull-ups, reducing BOM count and board space.

The integrated 30 Ω series termination resistors dampen signal reflections on high-speed traces, while IOFF functionality disables outputs during power-down to prevent backflow current. Schmitt-trigger inputs tolerate slow-rising signals and improve noise margin across temperature ranges from −40 °C to +125 °C.

Key Specifications

Pinout & Package

TSSOP48 (SOT362-1) package: plastic thin shrink small outline, 48 leads, 6.1 mm body width, 0.5 mm pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with SN74LVC16373ADGGR and 74ALVCH162373T, the 74LVCH162373ADGG:1 uniquely combines bus hold, on-die termination, and ultra-low-voltage operation (1.2 V), making it optimal for space-constrained, mixed-voltage, and low-power embedded systems where component count and signal integrity are critical.

Availability

74LVCH162373ADGG:1 is available at Aetrix Electronics and suitable for industrial PLC backplanes, FPGA I/O expansion modules, automotive body control units, and automated test equipment requiring stable component supply across extended temperature and mixed-voltage conditions.

Supply support for 74LVCH162373ADGG:1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVCH162373ADGG:1 belongs to Nexperia's advanced LVC/LVCH logic family, engineered specifically for low-voltage, high-speed, mixed-signal interface applications demanding robustness, integration, and wide operating margins.

FAQ

What is the function of the bus hold circuit in the 74LVCH162373ADGG:1?

The bus hold circuit actively maintains the last valid logic state on each data input (1D0–1D7, 2D0–2D7) when the input is un-driven or floating, eliminating the need for external pull-up or pull-down resistors. It draws ±75 μA at V_CC = 3.0 V and is disabled when input voltage exceeds V_CC, allowing safe 5.5 V overvoltage operation.

Can the 74LVCH162373ADGG:1 operate with a 1.2 V supply and still interface with 5 V signals?

Yes - the device is fully specified from 1.2 V to 3.6 V supply and features 5 V tolerant inputs/outputs. At 1.2 V V_CC, it accepts VI up to 5.5 V and drives VO compatible with 5 V TTL thresholds, enabling true bidirectional voltage translation without external level shifters.

How does the IOFF feature protect the device during partial power-down?

When V_CC = 0 V, the IOFF circuit disables all outputs and limits OFF-state leakage to ±20 μA even with 5.5 V applied to I/O pins. This prevents destructive back-current flow from powered sections into unpowered ones - a critical requirement for hot-swap, battery-backed, or multi-rail systems.

What is the purpose of the integrated 30 Ω series termination resistors?

The 30 Ω resistors are placed in series with each output (1Q0–1Q7, 2Q0–2Q7) to match typical PCB trace impedance and suppress signal reflections. This reduces overshoot, undershoot, and ringing on fast-switching digital lines, improving eye diagram integrity without requiring 16 discrete SMD resistors.