Nexperia USA Inc. 74LVCH16373ADL,112

Overview

74LVCH16373ADL,112 from Nexperia is a 16-bit D-type transparent latch with 3-state outputs, dual latch enable (1LE/2LE) and dual output enable (1OE/2OE), 5 V tolerant I/O, bus hold on data inputs, and IOFF partial power-down support. It operates from 1.2 V to 3.6 V supply and functions as two independent 8-bit latches or one unified 16-bit latch in high-speed digital bus interfacing applications.

For engineers reviewing the 74LVCH16373ADL,112 datasheet, 74LVCH16373ADL,112 pinout, 74LVCH16373ADL,112 application, or 74LVCH16373ADL,112 equivalent, this device is selected for mixed-voltage 3.3 V/5 V system-level data latching, address/data bus isolation, and noise-immune I/O buffering where Schmitt-trigger inputs and bus-hold stability eliminate external pull resistors.

Technical Context

This latch implements two independent 8-bit transparent latch sections, each controlled by dedicated LE and OE signals, enabling selective capture and tri-state control of half the data path without affecting the other. Its CMOS architecture supports rail-to-rail input thresholds defined per JEDEC standards (JESD8-7A/5A/C), with Schmitt-trigger inputs ensuring robust operation under slow edge rates.

The IOFF circuit actively disables outputs during power-down to prevent backflow current, while integrated bus hold on all D-inputs maintains valid logic states when inputs float-eliminating need for external biasing. Input tolerance up to 5.5 V allows direct interfacing with 5 V TTL or LVTTL sources even when VCC = 1.2 V–3.6 V.

Key Specifications

Pinout & Package

TSSOP48 package (SOT362-1), 48-pin plastic thin shrink small outline, 6.1 mm body width, 0.5 mm lead pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with 74LVC16373ADGG and SN74ALVCH16373GR, the 74LVCH16373ADL,112 uniquely combines bus hold, IOFF, and 1.2 V operation - making it the sole option for ultra-low-voltage, hot-swap-capable, and floating-input-resilient 16-bit latching.

Availability

74LVCH16373ADL,112 is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive ADAS sensor hubs, embedded test equipment, and medical imaging data acquisition boards requiring stable component supply across extended temperature and mixed-voltage conditions.

Supply support for 74LVCH16373ADL,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with leadership in automotive-qualified components and energy-efficient packaging.

The 74LVCH16373ADL,112 belongs to Nexperia's advanced LVC/LVCH logic family, engineered specifically for robust mixed-voltage system interfacing where bus hold, IOFF, and wide VCC range reduce design complexity and improve field reliability.

FAQ

Does 74LVCH16373ADL,112 support 1.2 V operation with full functionality?

Yes. The device is fully specified down to 1.2 V VCC, including guaranteed propagation delay (12 ns max), input thresholds (VIH = 1.08 V min), and bus hold operation. All DC and AC parameters in Table 5 and Table 6 are validated across 1.2 V–3.6 V, with no derating required at minimum supply.

Can 1OE and 2OE be tied together for single 16-bit 3-state control?

Yes. Pins 1 (1OE) and 24 (2OE) may be connected to a common control line. This configures both 8-bit sections identically - all 16 outputs enter high-impedance simultaneously when OE is HIGH. No timing or electrical conflict arises, as OE inputs are purely combinational and do not interact with latch state.

What is the maximum capacitive load the outputs can drive reliably?

The outputs are characterized up to 50 pF load capacitance (per Table 9 test conditions). At VCC = 3.3 V and CL = 50 pF, tPLH/tPHL remains ≤4.4 ns and tPZL/tPHZ ≤6.5 ns. Driving >50 pF may increase propagation delay and skew but does not violate absolute ratings - layout-dependent signal integrity analysis is recommended.

How does bus hold behave when an input exceeds VCC?

Per datasheet note [2], the bus hold circuit disables automatically when VI > VCC, allowing safe 5.5 V input application without contention. In that state, the input behaves as a standard CMOS gate with ±0.1 μA leakage - no current flows through the bus hold transistor, eliminating risk of latch-up or excessive power draw.