STMicroelectronics 74LVQ373MTR
- Part No.:
- 74LVQ373MTR
- Manufacturer:
- STMicroelectronics
- Category:
- Latches
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
74LVQ373MTR.pdf
- Description:
- IC D-TYPE TRANSP SGL 8:8 20SO
- Quantity:
- Payment:

- Shipping:

Inventory:4,043
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Product details
Overview
74LVQ373MTR from STMicroelectronics is a low-voltage CMOS octal D-type transparent latch with 3-state non-inverting outputs, operating from 2.0 V to 3.6 V. It features 5.8 ns typical propagation delay at 3.3 V, ±12 mA symmetrical output drive, and 75 Ω transmission line drive capability-ideal for PCI bus interfacing and low-noise 3.3 V digital systems.
For engineers reviewing the 74LVQ373MTR datasheet, 74LVQ373MTR pinout, 74LVQ373MTR application, or 74LVQ373MTR equivalent, key selection criteria include latch enable (LE) and output enable (OE) timing control, high-impedance output behavior, 3-state drive strength at 24 mA, and ESD immunity up to 2 kV.
Technical Context
This device implements an edge-triggered transparent latch architecture where Q outputs follow D inputs while LE is HIGH, and hold data when LE transitions LOW. Output state is controlled independently by OE: LOW enables normal logic-level outputs; HIGH places all eight outputs in high-impedance mode.
It uses sub-micron C2MOS technology with double-layer metal wiring, delivering balanced tPLH ≅ tPHL propagation delays, 0.4 V typical dynamic quiet output noise (VOLP), and guaranteed PCI bus voltage levels at 24 mA sink/source-enabling direct interface with legacy and mixed-voltage backplanes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 3.6 V - supports 3.3 V systems with 1.2 V data retention during standby |
| Propagation Delay (tPD) | 5.8 ns (typ.) at VCC = 3.3 V - enables ≤172 MHz latch-to-latch timing in synchronous designs |
| Output Drive Strength | ±12 mA (min.) at VCC = 3.0 V - ensures robust 75 Ω transmission line termination without external resistors |
| Quiescent Current (ICC) | 4 µA (max.) at TA = 25°C - suitable for battery-backed or ultra-low-power hold modes |
| ESD Immunity | 2 kV HBM - protects against handling-induced static discharge in assembly and field environments |
| Input/Output Capacitance | CIN = 4 pF, COUT = 8 pF - minimizes capacitive loading on driving gates and bus lines |
Pinout & Package
74LVQ373MTR is housed in a 20-pin SOIC (Small Outline Integrated Circuit) package, tape-and-reel format, with 1.27 mm pitch and standard SO-20 mechanical dimensions (13.00 × 7.60 mm body).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE | Active-low 3-state output enable - controls simultaneous high-impedance entry/exit for all eight outputs |
| 2,5,6,9,12,15,16,19 | Q0–Q7 | Non-inverting latched outputs - driven only when OE = LOW; otherwise high-Z |
| 3,4,7,8,13,14,17,18 | D0–D7 | Data inputs - sampled and held on LE falling edge; no internal storage without LE assertion |
| 11 | LE | Latch enable - transparent when HIGH; captures D-input state on transition to LOW |
| 10 | GND | Ground reference - shared return path for all I/O and supply currents |
| 20 | VCC | Positive supply - powers internal logic and output drivers; must be decoupled locally |
Key Features
| Feature | Design Value |
|---|---|
| Symmetrical output drive | |IOH| = |IOL| ≥ 12 mA at 3.0 V - eliminates skew between rising/falling edges on shared buses |
| Low dynamic noise | VOLP = 0.4 V (typ.) at 3.3 V - reduces ground bounce and crosstalk in dense PCB layouts |
| PCI bus compliance | Guaranteed 24 mA drive at PCI voltage thresholds - enables direct connection to PCI slots without level shifters |
| Pin-compatible upgrade | Drop-in replacement for 74LS373 and 74HC373 - preserves existing PCB layout and firmware logic |
Applications
| Industrial PLC I/O Expansion | PCI Bus Interface Buffering |
|---|---|
Use Scenario: Latching parallel sensor data from 8-bit ADCs or GPIO expanders before CPU read cycles in programmable logic controllers. IC Role / Device Role / Timing Role: Transparent latch synchronizing asynchronous peripheral data to system clock domain via LE edge capture. Use Value: Enables deterministic sampling with <12 ns max propagation delay and 1.5 ns min setup/hold - critical for cycle-accurate I/O timing. | Use Scenario: Isolating and buffering address/data lines between PCI host bridge and add-in cards in embedded computing platforms. IC Role / Device Role / Timing Role: 3-state bus transceiver supporting PCI's shared-bus arbitration protocol via OE-controlled tristate control. Use Value: Delivers 24 mA sink/source at PCI-compliant VOH/VOL levels - eliminates need for external bus terminators or level translators. |
| Low-Power Memory Address Latching | Legacy ISA Bus Data Capture |
Use Scenario: Holding memory address bits during multi-cycle DRAM access sequences in portable instrumentation with 3.3 V supply rails. IC Role / Device Role / Timing Role: Low-quiescent-current (4 µA max) latch maintaining address stability between memory controller phases. Use Value: Reduces standby power by >95% vs. 74LS373 while retaining identical timing margins and pinout. | Use Scenario: Capturing 8-bit ISA bus data during I/O port reads in retro-computing or industrial control adapters. IC Role / Device Role / Timing Role: TTL-compatible input thresholds and 3.3 V–5 V tolerant outputs enabling mixed-voltage ISA subsystem design. Use Value: Supports 5 V-tolerant operation via VIH/VIL specs (2.0 V/0.8 V) - allows safe interfacing with 5 V ISA masters without clamping diodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal transparent latch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC373PW | Lower ICC (1 µA typ.), smaller TSSOP20 package (4.4 × 6.5 mm), but reduced VOLP (0.3 V typ.) | Better suited for space-constrained portable designs; less effective for high-noise industrial backplanes | Select when board area is critical and noise margin >0.1 V is acceptable |
| SN74LVTH373PWR | TTL-compatible 3.3 V supply, higher drive (±32 mA), but ICC = 20 µA (max) and no 1.2 V data retention | Preferred for high-speed bus buffering requiring stronger drive; unsuitable for battery-hold applications | Select when driving long traces or multiple loads; avoid if low standby power is mandatory |
Compared with 74LVC373PW and SN74LVTH373PWR, the 74LVQ373MTR uniquely balances ultra-low quiescent current (4 µA), 2 kV ESD protection, and PCI-compliant 24 mA drive-making it optimal for industrial backplane interfaces where reliability, power, and signal integrity are jointly constrained.
Availability
74LVQ373MTR is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, PCI bus interface buffering, and low-power memory address latching requiring stable component supply across extended temperature ranges (−55°C to +125°C).
Supply support for 74LVQ373MTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and discrete components for automotive, industrial, and consumer markets.
The 74LVQ series targets low-voltage, low-noise digital logic applications-specifically engineered for 3.3 V system interoperability, ESD-hardened operation, and drop-in compatibility with legacy 74-series logic families.
FAQ
What is the maximum clock frequency supported by the 74LVQ373MTR?
The 74LVQ373MTR is not a clocked register but a transparent latch controlled by LE. Its usable data rate depends on LE pulse width (≥4.0 ns min at 3.3 V) and propagation delay (≤12.0 ns max). In practice, it supports reliable operation up to ~80 MHz for burst-mode latching when paired with appropriate setup/hold timing margins.
Can the 74LVQ373MTR operate with a 5 V supply?
No. Absolute maximum VCC is +7 V, but recommended operating range is strictly 2.0 V to 3.6 V. Applying 5 V exceeds specification and risks permanent damage. For 5 V systems, use 74LS373 or 74HCT373 instead-those feature TTL-compatible inputs and 5 V supply tolerance.
How does the 74LVQ373MTR handle simultaneous switching outputs (SSO) noise?
It mitigates SSO noise via low dynamic quiet output voltage (VOLP = 0.4 V typ. at 3.3 V) and symmetrical output impedance. The 75 Ω transmission line drive capability further suppresses reflections and ringing-reducing ground bounce compared to standard CMOS latches under heavy bus switching.
Is the 74LVQ373MTR RoHS compliant and halogen-free?
Yes. Per STMicroelectronics' official product change notices (PCN 12-0127), the 74LVQ373MTR manufactured after July 2004 meets RoHS Directive 2011/65/EU and is halogen-free per IEC 61249-2-21, with lead-free matte tin terminations and green molding compound.
74LVQ373MTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- 74LVQ
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 8:8
- Output Type:
- Tri-State
- Voltage - Supply:
- 2V ~ 3.6V
- Independent Circuits:
- 1
- Delay Time - Propagation:
- 5.8ns
- Current - Output High, Low:
- 24mA, 24mA
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SO
74LVQ373MTR FAQ
1.How can I place an order for 74LVQ373MTR through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVQ373MTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVQ373MTR reliable?
The price and inventory of 74LVQ373MTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVQ373MTR is usually 5 days.
3.What payment methods are accepted for 74LVQ373MTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVQ373MTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVQ373MTR?
74LVQ373MTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVQ373MTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVQ373MTR?
For technical support, including 74LVQ373MTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVQ373MTR requirements.
6.How does Aetrix verify that 74LVQ373MTR is sourced from the original manufacturer or authorized distributors?
All 74LVQ373MTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVQ373MTR meets industry standards.
7.What is the process for return or replacement of 74LVQ373MTR?
All 74LVQ373MTR units undergo pre-shipment inspection (PSI). If there is an issue with 74LVQ373MTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVQ373MTR part is unused and in its original packaging.
Return procedure for 74LVQ373MTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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