NXP Semiconductors 74LVT16373ADGG,112

Overview

74LVT16373ADGG,112 from Nexperia is a 3.3 V 16-bit transparent D-type latch with 3-state outputs, designed for high-speed bus interface and data buffering in digital systems. It functions as two independent 8-bit latches (each with dedicated LE/OE controls), supports 2.7–3.6 V supply, delivers ±64 mA/±32 mA output drive, and features bus-hold inputs eliminating external pull-ups. It is used in industrial control backplanes and memory address/data bus isolation.

For engineers reviewing the 74LVT16373ADGG,112 datasheet, 74LVT16373ADGG,112 pinout, 74LVT16373ADGG,112 application, or 74LVT16373ADGG,112 equivalent, this page provides verified functional behavior, TSSOP48 package mapping, timing-critical propagation delays (tPLH/tPHL ≤ 3.9 ns at 3.3 V), bus-hold current specs, and direct TTL-level compatibility without level-shifting.

Technical Context

The device implements dual 8-bit transparent latching logic with separate active-HIGH latch enables (1LE, 2LE) and active-LOW output enables (1OE, 2OE), enabling independent control of two 8-bit data channels. Its BiCMOS architecture delivers TTL-compatible input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) and overvoltage-tolerant inputs up to 5.5 V.

IOFF circuitry ensures partial power-down operation with <±100 μA off-state leakage, while bus-hold functionality maintains stable logic states on unused inputs (IBHL = 75–135 μA LOW, IBHH = −75–−135 μA HIGH at 3 V). Latch set-up time is 1.5 ns (HIGH) and 2.0 ns (LOW) at 3.0–3.6 V.

Key Specifications

Pinout & Package

TSSOP48 plastic thin shrink small outline package (SOT362-1), 48-pin, 6.1 mm body width, 0.5 mm pitch - optimized for high-density PCB layouts with thermal and mechanical reliability in reflow-soldered industrial assemblies.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with SN74LVC16373ADGGR and 74ALVCH16373PAG, the 74LVT16373ADGG,112 uniquely combines 5.5 V input tolerance, ±64 mA drive, and integrated bus-hold - making it the only option for robust 3.3 V/5 V mixed-bus latching without added components.

Availability

74LVT16373ADGG,112 is available at Aetrix Electronics and suitable for industrial backplane buffering, memory address latching, legacy bus interfacing, and test equipment signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LVT16373ADGG,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVT series targets high-speed 3.3 V digital interfacing, emphasizing robustness in mixed-voltage systems, bus integrity, and industrial-grade thermal performance - not general-purpose logic.

FAQ

Can 74LVT16373ADGG,112 be used with a 5 V microcontroller driving its inputs?

Yes - its inputs tolerate up to 5.5 V regardless of VCC (2.7–3.6 V), allowing direct connection to 5 V microcontrollers without level shifters. This is confirmed in Table 4 (VI max = +7.0 V) and Section 2 (overvoltage tolerant inputs to 5.5 V). No current-limiting resistors are needed.

What happens to outputs during power-up or power-down sequences?

The device features power-up 3-state and IOFF circuitry: outputs remain in high-impedance until VCC reaches valid operating range, and IOFF limits leakage to ±100 μA when VCC = 0 V. This prevents bus contention and backfeeding during sequencing - verified in Sections 2 and 9 (IOFF, power-up 3-state).

How does bus-hold eliminate external pull-up resistors?

Each data input has internal bus-hold circuitry drawing ±75–135 μA to maintain its last-valid logic state when floating. At 3 V supply, this holds inputs at VIH ≥ 2.0 V or VIL ≤ 0.8 V - meeting TTL thresholds without external resistors (Section 2, Table 6 IBHL/IBHH).

Is the 74LVT16373ADGG,112 pin-compatible with older 74LVT16373 variants?

Yes - the TSSOP48 (SOT362-1) package and pinout match all 74LVT16373A variants including 74LVT16373ADL (SSOP48) and 74LVT16373APAG (TSSOP48). Pin numbering, function assignment, and electrical specs are identical per Rev. 6 datasheet Section 5.1 and Table 2.