Nexperia USA Inc. 74LVT16373ADGG,118

Overview

74LVT16373ADGG,118 from Nexperia is a 3.3 V 16-bit transparent D-type latch with 3-state outputs, dual independent 8-bit latch sections (1LE/2LE and 1OE/2OE), bus-hold inputs eliminating external pull-ups, ±64 mA/–32 mA output drive, and operation from –40 °C to +85 °C. It serves as a bidirectional data latching interface in high-speed digital systems such as memory address/data bus isolation and FPGA I/O expansion.

For engineers reviewing the 74LVT16373ADGG,118 datasheet, 74LVT16373ADGG,118 pinout, 74LVT16373ADGG,118 application, or 74LVT16373ADGG,118 equivalent, key selection criteria include latch enable timing (t_su = 1.5 ns, t_h = 1.0 ns), 3-state propagation delays (t_PZH = 2.8 ns), overvoltage-tolerant 5.5 V inputs, and TSSOP48 package compatibility with dense PCB layouts.

Technical Context

The device implements two independent 8-bit transparent latches using BiCMOS logic, each controlled by dedicated active-HIGH latch enables (1LE, 2LE) and active-LOW output enables (1OE, 2OE). Latch transparency occurs when nLE is HIGH, allowing real-time D-to-Q tracking; data is captured on the HIGH-to-LOW transition of nLE with setup/hold times specified at 1.5 ns and 1.0 ns respectively.

Bus-hold circuitry maintains stable logic states on unused data inputs without external resistors, while IOFF protection enables partial power-down mode during VCC = 0 V. Overvoltage tolerance up to 5.5 V on all inputs permits safe interfacing with 5 V buses, and the 3-state outputs support shared-bus architectures with zero current loading when tied to 5 V rails.

Key Specifications

Pinout & Package

TSSOP48 plastic thin shrink small outline package (SOT362-1), 48-pin, 6.1 mm body width, 0.5 mm pitch - optimized for high-density PCB routing and automated assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit transparent latch applications.

Compared with SN74LVC16373A and 74ALVCH16373, the 74LVT16373ADGG,118 uniquely combines 5.5 V input tolerance, bus-hold, and IOFF in a single 3.3 V latch - making it the only option for industrial hot-swap and mixed-voltage bus isolation without additional support circuitry.

Availability

74LVT16373ADGG,118 is available at Aetrix Electronics and suitable for memory address latching, FPGA I/O expansion, PCI bus interfacing, and ATE signal conditioning requiring stable component supply across industrial temperature ranges and long-lifecycle programs.

Supply support for 74LVT16373ADGG,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for industrial and consumer applications.

The 74LVT series targets high-speed 3.3 V digital interfacing, emphasizing robustness in mixed-voltage systems, bus integrity, and thermal resilience for demanding embedded control and data acquisition platforms.

FAQ

What is the maximum clock frequency supported by the 74LVT16373ADGG,118?

The device does not operate on a clock signal but functions as a transparent latch triggered by the HIGH-to-LOW transition of LE. Its usable data rate is determined by propagation delay (1.8 ns typical) and setup/hold timing (1.5 ns / 1.0 ns), enabling reliable operation with input signal edges up to approximately 350 MHz in well-designed PCB layouts with controlled impedance.

Can the 74LVT16373ADGG,118 be used with a 5 V microcontroller?

Yes - all inputs (D, LE, OE) tolerate up to 5.5 V regardless of VCC (2.7–3.6 V), allowing direct connection to 5 V microcontrollers. Outputs swing between GND and VCC (3.3 V), so external level translation is required if driving 5 V logic inputs, but bus-hold and overvoltage protection eliminate damage risk during interfacing.

Does the 74LVT16373ADGG,118 require external pull-up resistors on unused inputs?

No - integrated bus-hold circuitry actively maintains the last-valid logic state on all data inputs (1D0–1D7, 2D0–2D7) without external components. This feature eliminates BOM items, saves PCB area, and prevents floating-input-induced noise or false triggering in partially utilized configurations.

How does the IOFF feature function during power-down sequences?

When VCC drops to 0 V, IOFF circuitry disables internal paths between inputs and outputs, limiting leakage current to ±100 μA even with inputs or outputs held at up to 4.5 V. This prevents back-powering of the VCC rail and ensures safe hot-swap operation in modular systems where boards may be inserted or removed while other slots remain powered.