Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Latches

STMicroelectronics 74LVX373MTR

Name: 74LVX373MTR
Brand: STMicroelectronics
SKU: 74LVX373MTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74LVX373MTR

Manufacturer:: STMicroelectronics

Category:: Latches

Package:: 20-SOIC (0.295", 7.50mm Width)

Datasheet:: 74LVX373MTR.pdf

Description:: IC D-TYPE TRANSP SGL 8:8 20SO

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,123

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74LVX373MTR from STMicroelectronics is a low-voltage CMOS octal D-type transparent latch with 3-state non-inverting outputs, 5V-tolerant inputs, 2V–3.6V operating range, 5.8ns typical propagation delay at 3.3V, and 4µA max quiescent current at 25°C. It serves as a data latching and bus isolation interface in 3.3V systems interfacing legacy 5V logic.

For engineers reviewing the 74LVX373MTR datasheet, 74LVX373MTR pinout, 74LVX373MTR application, or 74LVX373MTR equivalent, key selection criteria include 5V input tolerance, symmetrical 4mA output drive, high-impedance tri-state control via OE/LE, and latch timing parameters (tPLH/tPHL ≈ 5.8–10.3ns) under 3.3V operation.

Technical Context

The 74LVX373MTR implements an 8-bit transparent latch architecture where Q outputs follow D inputs when LE is HIGH, and hold the last D state when LE transitions LOW. Its dual enable structure-LE for data capture and OE for output gating-enables precise bus arbitration in shared-data-path systems.

All inputs feature power-down protection and accept 0–7V regardless of VCC, enabling safe 5V-to-3.3V level translation without external resistors. The device uses sub-micron C2MOS technology to achieve balanced tPLH/tPHL delays and low dynamic noise (VOLP = 0.3V typ at 3.3V).

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Operating Range	2.0V to 3.6V - supports battery-powered and mixed-voltage 3.3V systems with 1.2V data retention
t_PD (LE→Q)	5.8ns typ @ 3.3V - enables high-speed data capture in ≤100MHz bus cycles
I_OH/I_OL	±4mA min @ 3V - drives standard TTL loads and multiple CMOS inputs without buffering
V_IL/V_IH	0.8V / 2.0V @ 3V - ensures robust noise margin and compatibility with 5V logic thresholds
I_CC (Quiescent)	4µA max @ 25°C - minimizes standby power in portable and always-on embedded controllers
V_OHP/V_OLP	0.3V typ low-noise quiet output - reduces ground bounce and crosstalk in dense PCB layouts
Input Tolerance	0–7V independent of V_CC - eliminates level-shifter components in 5V↔3.3V interface designs

Pinout & Package

SOP-20 (Small Outline Package, 20-pin, tape-and-reel format), compliant with JEDEC MS-013, body width 7.5mm, pitch 1.27mm.

Pin/Terminal	Circuit Role	Design Meaning
1	OE	Active-low 3-state output enable - disables all Q outputs to high-impedance when HIGH
2,5,6,9,12,15,16,19	Q0–Q7	Non-inverting latched outputs - driven only when OE = LOW and LE has captured D state
3,4,7,8,13,14,17,18	D0–D7	Data inputs - sampled on LE transition from HIGH to LOW; 5V tolerant
11	LE	Latch enable - transparent mode when HIGH; latches D inputs on falling edge
10	GND	Ground reference - must be connected to system 0V plane for stable noise immunity
20	V_CC	Positive supply - powers internal logic; accepts 2.0–3.6V; decoupling capacitor required

Key Features

Feature	Design Value
5V-tolerant inputs	Accepts 0–7V signals regardless of V_CC, enabling direct connection to 5V microcontrollers or FPGAs
Power-down input protection	Prevents back-powering and latch-up during V_CC ramp-up/down or hot-insertion scenarios
Balanced propagation delays	t_PLH ≈ t_PHL minimizes duty-cycle distortion in clocked data paths
2kV ESD immunity	HBM-rated protection on all pins reduces need for external TVS diodes in industrial environments
Low dynamic noise (VOLP)	0.3V typical quiet-output voltage suppresses simultaneous switching noise in multi-latch buses

Applications

Industrial PLC I/O Expansion

Embedded Microcontroller Bus Interface

Use Scenario: Latching parallel sensor data from 8-bit ADCs before CPU read in programmable logic controllers.

IC Role / Device Role / Timing Role: Data capture latch synchronized to LE edge; OE controlled by microcontroller address decode.

Use Value: Enables deterministic sampling window and isolates ADC bus from CPU bus contention using 3-state outputs.

Use Scenario: Interfacing a 3.3V ARM Cortex-M3 GPIO port with legacy 5V peripheral ICs (e.g., LCD controllers, DACs).

IC Role / Device Role / Timing Role: Voltage-level translating latch with bidirectional timing control via LE/OE.

Use Value: Eliminates discrete level shifters while maintaining 5.8ns timing integrity and <4µA sleep current.

Portable Medical Instrument Data Buffering

Automotive Body Control Module (BCM) Signal Conditioning

Use Scenario: Holding patient vital sign measurements from analog front-end during low-power sleep mode in handheld monitors.

IC Role / Device Role / Timing Role: Low-power data retention latch; operates down to 2.0V with 1.2V data hold capability.

Use Value: Extends battery life via 4µA quiescent current and avoids data loss during brown-out conditions.

Use Scenario: Isolating CAN transceiver TX/RX lines from MCU GPIOs during firmware updates or reset sequences.

IC Role / Device Role / Timing Role: Tri-state bus buffer with fast output disable (t_PHZ = 8.2ns typ @ 3.3V).

Use Value: Prevents spurious CAN frames during MCU reinitialization by cleanly disabling outputs within one clock cycle.

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal latch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74LVC373PW,118 (Nexperia)	Wider V_CC range (1.65–3.6V); lower t_PD (4.2ns typ); no 5V tolerance on inputs without external clamping	Requires external series resistors for 5V input protection; better suited for pure 3.3V/2.5V systems	Select when absolute minimum propagation delay is critical and 5V inputs are absent or conditioned
SN74LV373APWR (TI)	Identical 2–3.6V range and 5V-tolerant inputs; higher I_OL (16mA min); ICC = 10µA max - 2.5× higher quiescent current	Higher drive strength supports heavier capacitive loads but increases standby power in battery systems	Select when driving >40pF traces or multiple loads is required, and 10µA ICC is acceptable

Compared with 74LVX373MTR, the Nexperia part offers faster speed but sacrifices native 5V input robustness, while the TI part delivers stronger output drive at the cost of higher static power - making the STMicroelectronics device optimal for low-noise, low-power 5V↔3.3V bridging where timing and efficiency are balanced.

Availability

74LVX373MTR is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, embedded microcontroller bus interface, and portable medical instrument data buffering requiring stable component supply across extended temperature ranges (–55°C to +125°C).

Supply support for 74LVX373MTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management ICs with strong analog and mixed-signal design heritage.

The 74LVX series targets low-voltage, low-power logic applications in battery-operated and noise-sensitive 3.3V systems, emphasizing 5V tolerance, ESD robustness, and sub-micron process efficiency.

FAQ

Can 74LVX373MTR operate reliably at 2.0V supply?

Yes - the device is fully specified from 2.0V to 3.6V per Table 5. At 2.0V, VIH is guaranteed ≥1.5V and VIL ≤0.5V, supporting clean logic thresholds. Propagation delay increases to 14.5ns max (tPLH/tPHL), and output drive drops to ±2mA, but all DC and AC parameters remain valid across –55°C to +125°C.

What happens to outputs when V_CC is unpowered?

When V_CC = 0V, all outputs enter high-impedance state regardless of OE/LE states due to internal power-down protection circuitry. Inputs tolerate up to 7V without damage or back-driving, preventing unintended current flow into the unpowered IC - critical for hot-swap and partial-power-down systems.

Is the 74LVX373MTR pin-compatible with standard 74HC373?

No - although functionally identical and pin-for-pin compatible with 74-series 373 logic, the 74LVX373MTR uses different DC thresholds (VIH/VIL optimized for 3.3V) and lacks 5V supply capability. It is not a drop-in replacement for 74HC373 in 5V systems, but matches 74LV373 and 74LVC373 pinouts in SOP-20 packages.

How does the latch handle simultaneous LE and OE transitions?

The truth table defines priority: OE controls output state independently of LE. When OE goes HIGH, outputs go high-impedance immediately - even if LE is active. When OE returns LOW, outputs resume their latched state (not transparent mode), ensuring no bus glitches during enable sequencing. This behavior is verified in Figure 3's logic diagram and Table 3.

74LVX373MTR Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: 74LVX

Package/Case:: 20-SOIC (0.295", 7.50mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: D-Type Transparent Latch

Circuit:: 8:8

Output Type:: Tri-State

Voltage - Supply:: 2V ~ 3.6V

Independent Circuits:: 1

Delay Time - Propagation:: 8.5ns

Current - Output High, Low:: 4mA, 4mA

Operating Temperature:: -55°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 20-SO

74LVX373MTR FAQ

1.How can I place an order for 74LVX373MTR through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LVX373MTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LVX373MTR reliable?

The price and inventory of 74LVX373MTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVX373MTR is usually 5 days.

3.What payment methods are accepted for 74LVX373MTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVX373MTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LVX373MTR?

74LVX373MTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LVX373MTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LVX373MTR?

For technical support, including 74LVX373MTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVX373MTR requirements.

6.How does Aetrix verify that 74LVX373MTR is sourced from the original manufacturer or authorized distributors?

All 74LVX373MTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVX373MTR meets industry standards.

7.What is the process for return or replacement of 74LVX373MTR?

All 74LVX373MTR units undergo pre-shipment inspection (PSI). If there is an issue with 74LVX373MTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LVX373MTR part is unused and in its original packaging.

Return procedure for 74LVX373MTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…