Allegro MicroSystems A4919GETTR-T

Overview

A4919GETTR-T from Allegro MicroSystems is a three-phase N-channel MOSFET gate driver IC with integrated charge pump, sleep mode, and 5.5–50 V supply range. It delivers high-current gate drive to external power MOSFETs in BLDC motor bridges, supports bootstrap-based high-side operation down to 5.5 V, and provides short-circuit detection on all six phases for battery-powered power tools and CPAP machines.

For engineers reviewing the A4919GETTR-T datasheet, A4919GETTR-T pinout, A4919GETTR-T application, or A4919GETTR-T equivalent, this page details confirmed electrical specs (e.g., 13 V VREG output, 2.4 Ω typical low-side R_DS(on), 90 ns propagation delay), thermal resistance (32 °C/W for QFN), fault diagnostics (VDSTH-programmable threshold), and validated alternative part options.

Technical Context

The A4919GETTR-T implements a charge pump regulator to sustain >10 V gate drive at V_BB ≥ 7 V and functional operation down to 5.5 V with reduced drive. Its six independent TTL-compatible logic inputs (AHI/ALO through CHI/CLO) enable arbitrary commutation schemes managed externally by a microcontroller.

Integrated protection includes per-phase drain-source voltage monitoring via programmable VDSTH pin (0.2–2.0 V range), crossover control to prevent shoot-through, and open-drain FAULT output signaling short-to-supply, short-to-ground, undervoltage, or overtemperature events.

Key Specifications

Pinout & Package

Package: 28-terminal 5 mm × 5 mm × 0.90 mm QFN with exposed thermal pad (suffix ET, Pb-free, matte-tin plating).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar three-phase gate driver applications.

Compared with MP6532DJ-LF-Z and DRV8305PWP, the A4919GETTR-T offers unique programmable short-circuit detection (via VDSTH), ultra-low sleep current (≤15 µA), and optimized bootstrap architecture for wide-input battery tools - making it preferred for cost-sensitive, high-reliability portable motor systems without need for integrated current sensing or auxiliary LDOs.

Availability

A4919GETTR-T is available at Aetrix Electronics and suitable for battery-powered power tools, CPAP machines, and industrial grinders requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for A4919GETTR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Allegro MicroSystems is a U.S.-based designer of high-performance magnetic sensors and power ICs, specializing in motion control and energy-efficient semiconductor solutions for automotive and industrial markets.

The A4919 product line delivers robust three-phase gate drivers for brushless DC motors, engineered specifically for battery-operated equipment demanding high reliability, fault resilience, and wide-input voltage operation.

FAQ

What is the minimum V_BB supply voltage required for full gate drive performance in the A4919GETTR-T?

The A4919GETTR-T delivers full (>10 V) gate drive performance at V_BB ≥ 7 V using its internal charge pump regulator. At 5.5 V ≤ V_BB < 7 V, the device remains functional but provides reduced gate drive voltage - verified in Electrical Characteristics Table with V_REG dropping to 8.5–9.5 V at 5.5–6 V input. This behavior is explicitly documented for the A4919GETTR-T variant in the datasheet's "VREG Output Voltage" row.

Does the A4919GETTR-T include an integrated LDO regulator?

No, the A4919GETTR-T does not include an integrated LDO regulator. Per the Selection Guide table, the "Regulator" column for A4919GETTR-T is marked "–", confirming absence of 3.3 V or 5 V LDO output. The V3/V5 pins are unconnected internally; only the VDDM monitor function applies to non-LDO variants, and VDDM must be tied to system logic supply. This distinguishes A4919GETTR-T from A4919GETTR-3-T and A4919GETTR-5-T.

How is short-circuit detection implemented on the A4919GETTR-T, and can the threshold be adjusted?

The A4919GETTR-T implements per-phase short-to-supply and short-to-ground detection using drain-source voltage monitors on each external MOSFET. The detection threshold is set via the VDSTH pin: applying 0.2–2.0 V configures the exact trip point (e.g., 0.8 V for CPAP motor winding faults), with ±100 mV offset tolerance. If VDSTH < 0.1 V, detection is disabled; if >2.7 V, it defaults to internal 1.2 V threshold. This programmability is confirmed in the Electrical Characteristics and Functional Description sections.

What thermal performance can be expected from the A4919GETTR-T in its QFN package?

The A4919GETTR-T in its 5 mm × 5 mm QFN package (ET) has a junction-to-ambient thermal resistance (R_θJA) of 32 °C/W when mounted on a 4-layer PCB per JEDEC standards. Its junction-to-pad resistance (R_θJP) is 2 °C/W, confirming highly efficient heat transfer through the exposed thermal pad. These values are measured and published in the Thermal Characteristics table for the ET package variant, directly applicable to A4919GETTR-T.

Is sleep mode available on the A4919GETTR-T, and what triggers it?

Yes, sleep mode is available on the A4919GETTR-T. It activates after logic-low states (<0.5 V, per V_ILS) are detected simultaneously on all six control inputs (AHI, ALO, BHI, BLO, CHI, CLO) for ≥7.5 ms (t_SLT). In sleep mode, all gate outputs enter high-impedance state and quiescent current drops to ≤15 µA. Wake-up occurs within ≤1 ms (t_WK) of any input rising above VIH (2.0 V). This behavior is exclusive to non-LDO variants like A4919GETTR-T.